BD82HM55-SLGZS Просмотр технического описания (PDF) - Intel

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Компоненты Описание

производитель

BD82HM55-SLGZS

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel 

Contents

1

Introduction ............................................................................................................ 43

1.1 About This Manual ............................................................................................. 43

1.2 Overview ......................................................................................................... 47

1.3

1In.2te.1l®

5

SCeraipesabCilhitiypsOevt earnvdieIwn.t.e.l.®...3..4..0.0...S..e..r.i.e.s...C..h.i.p..s.e..t..S..K..U...D..e.f.i.n..i.t.i.o.n............................................

49

55

1.4 Reference Documents ........................................................................................ 57

2

Signal Description ................................................................................................... 59

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 61

2.2 PCI Express* .................................................................................................... 61

2.3 Firmware Hub Interface...................................................................................... 62

2.4 PCI Interface .................................................................................................... 63

2.5 Serial ATA Interface........................................................................................... 65

2.6 LPC Interface.................................................................................................... 68

2.7 Interrupt Interface ............................................................................................ 68

2.8 USB Interface ................................................................................................... 69

2.9 Power Management Interface.............................................................................. 71

2.10 Processor Interface............................................................................................ 74

2.11 SMBus Interface................................................................................................ 74

2.12 System Management Interface............................................................................ 75

2.13 Real Time Clock Interface ................................................................................... 75

2.14

2.15

MInitsecle®llaHnigehouDseSfiingintiaolns

........................................................................................

Audio Link .........................................................................

76

77

2.16 Controller Link .................................................................................................. 78

2.17

2.18

SInetreial®l

Peripheral Interface (SPI) ..........................................................................

Quiet System Technology and Thermal Reporting .........................................

78

79

2.19 JTAG Signals .................................................................................................... 80

2.20 Clock Signals .................................................................................................... 80

2.21 LVDS Signals (Mobile only) ................................................................................. 82

2.22

2.23

AInntaello®gFDleisxpiblaley

/CRT DAC Signals ........................................................................

Display Interface (FDI)..................................................................

83

84

2.24 Digital Display Signals........................................................................................ 84

2.25 General Purpose I/O Signals ............................................................................... 87

2.26 Manageability Signals ........................................................................................ 90

2.27 Power and Ground Signals .................................................................................. 91

2.28 Pin Straps ........................................................................................................ 93

2.28.1 Functional Straps ................................................................................ 93

2.28.2 External RTC Circuitry.......................................................................... 97

3

PCH Pin States......................................................................................................... 99

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 99

3.2 Output and I/O Signals Planes and States........................................................... 101

3.3 Power Planes for Input Signals .......................................................................... 112

4

System Clocks ....................................................................................................... 119

5

Functional Description ........................................................................................... 123

5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 123

5.1.1

PCI Bus Interface .............................................................................. 123

5.1.2

PCI Bridge As an Initiator ................................................................... 123

5.1.2.1

Memory Reads and Writes .................................................... 124

5.1.2.2

I/O Reads and Writes .......................................................... 124

5.1.2.3

Configuration Reads and Writes ............................................ 124

5.1.2.4

Locked Cycles ..................................................................... 124

5.1.2.5

Target / Master Aborts ......................................................... 124

5.1.2.6

Secondary Master Latency Timer ........................................... 124

5.1.2.7

Dual Address Cycle (DAC) .................................................... 124

5.1.2.8

Memory and I/O Decode to PCI ............................................. 125

5.1.3

Parity Error Detection and Generation .................................................. 125

5.1.4

PCIRST# .......................................................................................... 126

5.1.5

Peer Cycles ...................................................................................... 126

5.1.6

PCI-to-PCI Bridge Model..................................................................... 127

5.1.7

IDSEL to Device Number Mapping ....................................................... 127

Datasheet

3

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