BD82HM55-SLGZS Просмотр технического описания (PDF) - Intel
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BD82HM55-SLGZS Datasheet PDF : 956 Pages
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13.2
13.3
13.4
13.5
13.6
13.7
13.1.32 FWH_DEC_EN1—Firmware Hub Decode Enable
Register (LPC I/F—D31:F0) ................................................................ 487
13.1.33 BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)............................................................................. 489
13.1.34 FDCAP—Feature Detection Capability ID
Register (LPC I/F—D31:F0)................................................................ 490
13.1.35 FDLEN—Feature Detection Capability Length
Register (LPC I/F—D31:F0)................................................................ 490
13.1.36 FDVER—Feature Detection Version
Register (LPC I/F—D31:F0)................................................................ 490
13.1.37 FDVCT—Feature Vector Register
(LPC I/F—D31:F0)............................................................................. 491
13.1.38 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)............................................................................. 491
DMA I/O Registers........................................................................................... 492
13.2.1 DMABASE_CA—DMA Base and Current Address Registers ....................... 493
13.2.2 DMABASE_CC—DMA Base and Current Count Registers .......................... 494
13.2.3 DMAMEM_LP—DMA Memory Low Page Registers.................................... 494
13.2.4 DMACMD—DMA Command Register ..................................................... 495
13.2.5 DMASTA—DMA Status Register ........................................................... 495
13.2.6 DMA_WRSMSK—DMA Write Single Mask Register .................................. 496
13.2.7 DMACH_MODE—DMA Channel Mode Register ........................................ 497
13.2.8 DMA Clear Byte Pointer Register.......................................................... 498
13.2.9 DMA Master Clear Register ................................................................. 498
13.2.10 DMA_CLMSK—DMA Clear Mask Register ............................................... 498
13.2.11 DMA_WRMSK—DMA Write All Mask Register ......................................... 499
Timer I/O Registers ......................................................................................... 499
13.3.1 TCW—Timer Control Word Register...................................................... 500
13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ....................... 502
13.3.3 Counter Access Ports Register ............................................................. 503
8259 Interrupt Controller (PIC) Registers ........................................................... 503
13.4.1 Interrupt Controller I/O MAP ............................................................... 503
13.4.2 ICW1—Initialization Command Word 1 Register..................................... 504
13.4.3 ICW2—Initialization Command Word 2 Register..................................... 505
13.4.4 ICW3—Master Controller Initialization Command
Word 3 Register ................................................................................ 505
13.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register ................................................................................ 506
13.4.6 ICW4—Initialization Command Word 4 Register..................................... 506
13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register ........................................................................................... 507
13.4.8 OCW2—Operational Control Word 2 Register ......................................... 507
13.4.9 OCW3—Operational Control Word 3 Register ......................................... 508
13.4.10 ELCR1—Master Controller Edge/Level Triggered Register ........................ 509
13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register .......................... 510
Advanced Programmable Interrupt Controller (APIC)............................................ 511
13.5.1 APIC Register Map............................................................................. 511
13.5.2 IND—Index Register .......................................................................... 511
13.5.3 DAT—Data Register ........................................................................... 512
13.5.4 EOIR—EOI Register ........................................................................... 512
13.5.5 ID—Identification Register .................................................................. 513
13.5.6 VER—Version Register ....................................................................... 513
13.5.7 REDIR_TBL—Redirection Table ............................................................ 514
Real Time Clock Registers................................................................................. 516
13.6.1 I/O Register Address Map ................................................................... 516
13.6.2 Indexed Registers ............................................................................. 517
13.6.2.1 RTC_REGA—Register A ........................................................ 518
13.6.2.2 RTC_REGB—Register B (General Configuration)....................... 519
13.6.2.3 RTC_REGC—Register C (Flag Register) ................................... 520
13.6.2.4 RTC_REGD—Register D (Flag Register) .................................. 520
Processor Interface Registers ............................................................................ 521
13.7.1 NMI_SC—NMI Status and Control Register............................................ 521
13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
Register ........................................................................................... 522
13.7.3 PORT92—Fast A20 and Init Register .................................................... 522
13.7.4 COPROC_ERR—Coprocessor Error Register ........................................... 522
13.7.5 RST_CNT—Reset Control Register........................................................ 523
Datasheet
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