BD82HM55-SLGZS Просмотр технического описания (PDF) - Intel
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BD82HM55-SLGZS Datasheet PDF : 956 Pages
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12.1.22
12.1.23
12.1.24
12.1.25
12.1.26
12.1.27
12.1.28
12.1.29
12.1.30
DR—Data Register
(Gigabit LAN—D25:F0) ....................................................................... 463
CLIST 2—Capabilities List Register 2
(Gigabit LAN—D25:F0) ....................................................................... 463
MCTL—Message Control Register
(Gigabit LAN—D25:F0) ....................................................................... 463
MADDL—Message Address Low Register
(Gigabit LAN—D25:F0) ....................................................................... 464
MADDH—Message Address High Register
(Gigabit LAN—D25:F0) ....................................................................... 464
MDAT—Message Data Register
(Gigabit LAN—D25:F0) ....................................................................... 464
FLRCAP—Function Level Reset Capability
(Gigabit LAN—D25:F0) ....................................................................... 464
FLRCLV—Function Level Reset Capability Length and Version
(Gigabit LAN—D25:F0) ....................................................................... 465
DEVCTRL—Device Control (Gigabit LAN—D25:F0) .................................. 465
13 LPC Interface Bridge Registers (D31:F0) ............................................................... 467
13.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 467
13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ........................... 468
13.1.2 DID—Device Identification Register (LPC I/F—D31:F0)............................ 468
13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0).............................. 469
13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) .................................... 470
13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ......................... 471
13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) .......................... 471
13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) .................................. 471
13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) ................................. 471
13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ......................... 471
13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ............................... 472
13.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) .......................... 472
13.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0) ........................ 472
13.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)........................ 472
13.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) ............................ 473
13.1.15 GPIOBASE—GPIO Base Address Register
(LPC I/F—D31:F0) ............................................................................. 473
13.1.16 GC—GPIO Control Register (LPC I/F—D31:F0) ....................................... 474
13.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0) ............................................................................. 475
13.1.18 SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0) ............................................................................. 476
13.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0) ............................................................................. 477
13.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function Register
(LPC I/F—D31:F0) ............................................................................. 477
13.1.21 LPC_HnBDF—HPET n Bus:Device:Function Register
(LPC I/F—D31:F0) ............................................................................. 478
13.1.22 LPC_I/O_DEC—I/O Decode Ranges Register
(LPC I/F—D31:F0) ............................................................................. 479
13.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ............................. 480
13.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0) ............................................................................. 481
13.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0) ............................................................................. 481
13.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register
(LPC I/F—D31:F0) ............................................................................. 482
13.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register
(LPC I/F—D31:F0) ............................................................................. 482
13.1.28 ULKMC—USB Legacy Keyboard / Mouse Control
Register (LPC I/F—D31:F0) ................................................................ 483
13.1.29 LGMR—LPC I/F Generic Memory Range Register
(LPC I/F—D31:F0) ............................................................................. 484
13.1.30 FWH_SEL1—Firmware Hub Select 1 Register
(LPC I/F—D31:F0) ............................................................................. 485
13.1.31 FWH_SEL2—Firmware Hub Select 2 Register
(LPC I/F—D31:F0) ............................................................................. 486
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