GBE-PCS-PM-U1 Просмотр технического описания (PDF) - Lattice Semiconductor

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GBE-PCS-PM-U1

Gigabit Ethernet PCS IP Core for LatticeECP2M

Lattice Semiconductor 

Lattice Semiconductor

Gigabit Ethernet PCS IP Core

for LatticeECP2M

Simulation

To run the reference design simulation, do the following:

1. Open ModelSim.

2. Under the File tab, select Change Directory and choose folder

\<project_dir>\gbe_pcs_eval\<username>\sim\modelsim.

3. Under the Tools tab, select TCL _ Execute Macro and execute the ModelSim “do” script shown.

The simulation waveform results will be displayed in the ModelSim Wave window.

Implementation

To synthesize/map/place/route the reference design:

1. Select Open Project under the File tab in ispLEVER.

2. Browse to \<project_dir\gbe_pcs_eval\<username>\impl\reference in the Open Project dialog

box.

3. Select and open <username>_reference_eval.syn. A this point, all of the files needed to support top-level

synthesis and implementation will be imported to the project.

4. Select the device top-level entry in the left-hand GUI window.

5. Implement the complete design via the standard ispLEVER GUI flow.

Note that the implementation flow described here is only validated for use with the Synplicity synthesizer. The rea-

son for this is that some of the timing constraints are listed in the “physical” format. The names of these physical

preferences change when a different synthesizer is used. It is possible to use the Precision RTL synthesizer with

this reference design; however, you will have to rename the existing physical preferences into names compatible

with the Precision RTL synthesis output.

Reference Design Performance and Utilization

Table 6. Performance and Resource Utilization1

Target Device

LFE2M35E-5F672CES

SLICEs

1250

LUTs

1720

Registers

1321

EBRs

2

SERDES/PCS

1

I/Os fMAX (MHz)

31

125

1. Performance and utilization characteristics are in Lattice’s ispLEVER 7.0 software with Synplify synthesis. When using this IP core in a dif-

ferent software version or a different device density or speed grade, performance may vary.

References

• Technical Note 1124, LatticeECP2M SERDES/PCS Usage Guide

• LatticeECP2/M Family Data Sheet

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