GBE-PCS-PM-U1 Просмотр технического описания (PDF) - Lattice Semiconductor
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GBE-PCS-PM-U1 Datasheet PDF : 17 Pages
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Lattice Semiconductor
Gigabit Ethernet PCS IP Core
for LatticeECP2M
Figure 9. Block Diagram GbE Physical Layer Reference Design
125Mhz
Ref Clk
GMII
SERDES/PCS
8BI
8b10b
Encoder
Serializer
Loopback
GbE PCS
IP Core
MDIO
MDIO
Registers
Controller regbus
SCI
8b10b
Decoder De-Serializer
Link State Machine
JTAG
ORCAstra
Controller SCI
Ethernet
Physical Link
Frame
Driver
Frame
Monitor
GMII
8BI
GbE PCS
IP Core
Registers
regbus
SCI
8b10b
Encoder
Serializer
8b10b
Decoder De-Serializer
Link State Machine
IP Core Registers
A set of registers are implemented for each of the GbE PCS IP cores. These registers provide the management
control functions discussed in IEEE 802.3 clauses 22 and 37. The registers are most commonly associated with
managing auto-negotiation. The registers can be assessed by an external MDIO interface that conforms to the SMI
protocol in IEEE 802.3 clause 22 or the registers can be accessed by an external JTAG interface that conforms to
the Lattice ORCAstra protocol. The external pin enable_smi selects which register control method is used.
Table 3 shows the register set for one of the IP cores. Both IP cores have identical register sets. When using SMI,
the two cores are distinguished by using different port IDs. When using ORCAstra, the two cores are distinguished
by different memory address mappings.
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