GBE-PCS-PM-U1 Просмотр технического описания (PDF) - Lattice Semiconductor
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GBE-PCS-PM-U1 Datasheet PDF : 17 Pages
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Lattice Semiconductor
Gigabit Ethernet PCS IP Core
for LatticeECP2M
Table 3. GbE PCS IP Core Management Registers
Access
Address Mode
Register
Name
Register Bits
D15 D14 D13
D12
D11 D10
D9
D8 D7 D6
D5
D4 D3 D2
D1
D0
0x0
R/W
Control
— — mr_main_reset — — mr_restart_an — — —
—
———
—
—
0x1
R
Status
0
0
0
0
0
0
0
0
0
0 mr_an-complete 0
0
0
0
0
0x2
—
N/A
———
—
——
—
———
—
———
—
—
0x3
—
N/A
———
—
——
—
———
—
———
—
—
0x4
R/W
Auto-Negotiation
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mr_adv_ability[15:0]
0x5
R
Auto-Negotiation
Link Partner
mr_lp_adv_ability[15:0]
0x6
R
Auto-Negotiation
Expansion
0
0
0
0
0
0
0
0
0
0
0
0
0
0 mr_page_rx 0
LatticeECP2M Embedded SERDES/PCS Registers
The embedded SERDES/PCS has a large register set for managing control and status. These registers are auto-
matically configured for proper operation during FPGA configuration by means of an auto-configuration file called
pcs_serdes.txt. If you want the registers to maintain their auto-configured states, you do not need to manually
access the embedded SERDES/PCS registers. However, if you want to change register settings, or monitor the
status registers, then you must manually access the registers. This reference design employs an external JTAG
interface controlled by Lattice ORCAstra software for accessing the embedded SERDES/PCS registers. Table 4
shows the address mapping. Note that you may also access the GbE PCS IP core management registers through
the ORCAstra interface. Please consult technical note TN1124, LatticeECP2M SERDES/PCS Usage Guide, for
details on the embedded SERDES/PCS registers.
Table 4. ORCAstra Register Memory Map
ORCAstra Address
0x000 - 0x03F
0x400 - 0x07F
0x800 - 0x0BF
0xC00 - 0x0FF
0x100 - 0x13F
0x800 / 0x810
0x801 / 0x811
0x802 / 0x812
0x803 / 0x813
0x808 / 0x818
0x809 / 0x819
0x80A / 0x81A
0x80B / 0x81B
0x80C / 0x81C
0x80D / 0x81D
0x820
0x821
0x820
Register Description
Embedded SERDES/PCS – Channel 0 Registers
Embedded SERDES/PCS – Channel 1 Registers
Embedded SERDES/PCS – Channel 2 Registers
Embedded SERDES/PCS – Channel 3 Registers
Embedded SERDES/PCS – Quad Registers
IP Core 0 / IP Core 1 – control reg [7:0]
IP Core 0 / IP Core 1 – control reg [15:8]
IP Core 0 / IP Core 1 – status reg [7:0]
IP Core 0 / IP Core 1 – status reg [15:8]
IP Core 0 / IP Core 1 – mr_adv_ability [7:0]
IP Core 0 / IP Core 1 – mr_adv_ability [15:8]
IP Core 0 / IP Core 1 – mr_lp_adv_ability [7:0]
IP Core 0 / IP Core 1 – mr_lp_adv_ability [15:8]
IP Core 0 / IP Core 1 – mr_an_expansion [7:0]
IP Core 0 / IP Core 1 – mr_an_expansion [15:8]
Soft FPGA Logic ID Version Register 0 (Data = 0xAA)
Soft FPGA Logic ID Version Register 1 (Data = 0x55)
Soft FPGA Logic Control Register (bit D0 enables frame driver)
14
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