LHF16KAP Просмотр технического описания (PDF) - Sharp Electronics

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LHF16KAP

Flash Memory 16M (2MB × 8 / 1MB × 16))

Sharp Electronics 

sharp

LHF16KAP

8

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the

manufacturer code, device code, block status codes

for each block (see Figure 4). Using the manufacturer

and device codes, the system CPU can automatically

match the device with its proper algorithms. The

block status codes identify locked or unlocked block

setting and erase completed or erase uncompleted

condition.

1FFFFF

1F0006

1F0005

1F0004

1F0003

1F0000

1EFFFF

020000

01FFFF

010006

010005

010004

010003

010000

00FFFF

Reserved for

Future Implementation

Block 31 Status Code

Reserved for

Future Implementation

Block 31

(Blocks 2 through 30)

Reserved for

Future Implementation

Block 1 Status Code

Reserved for

Future Implementation

Block 1

Reserved for

Future Implementation

000006

000005

000004

000003

000002

000001

000000

Block 0 Status Code

Device Code

Manufacturer Code Block 0

Figure 4. Device Identifier Code Memory Map

3.6 Query Operation

The query operation outputs the query structure.

Query database is stored in the 48Byte ROM. Query

structure allows system software to gain critical

information for controlling the flash component.

Query structure are always presented on the lowest-

order data output (DQ0-DQ7) only.

3.7 Write

Writing commands to the CUI enable reading of

device data and identifier codes. They also control

inspection and clearing of the status register. When

VCC=VCC1/2 and VPP=VPPH1, the CUI additionally

controls block erase, full chip erase, (multi) word/byte

write and block lock-bit configuration.

The Block Erase command requires appropriate

command data and an address within the block to be

erased. The Word/byte Write command requires the

command and address of the location to be written.

Set Block Lock-Bit command requires the command

and block address within the device (Block Lock) to

be locked. The Clear Block Lock-Bits command

requires the command and address within the device.

The CUI does not occupy an addressable memory

location. It is written when WE# and CE# are active.

The address and data needed to execute a command

are latched on the rising edge of WE# or CE#

(whichever goes high first). Standard microprocessor

write timings are used. Figures 19 and 20 illustrate

WE# and CE#-controlled write operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK, Read operations from

the status register, identifier codes, query, or blocks

are enabled. Placing VPPH1 on VPP enables

successful block erase, full chip erase, (multi)

word/byte write and block lock-bit configuration

operations.

Device operations are selected by writing specific

commands into the CUI. Table 4 defines these

commands.

Rev. 2.0

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