LHF16KAP Просмотр технического описания (PDF) - Sharp Electronics

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производитель

LHF16KAP

Flash Memory 16M (2MB × 8 / 1MB × 16))

Sharp Electronics 

sharp

LHF16KAP

10

Table 4. Command Definitions(10)

Command

Bus Cycles Notes

First Bus Cycle

Second Bus Cycle

Req’d

Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)

Read Array/Reset

1

Write

X

FFH

Read Identifier Codes

≥2

4 Write

X

90H Read

IA

ID

Query

≥2

Write

X

98H Read QA

QD

Read Status Register

2

Write

X

70H Read

X

SRD

Clear Status Register

1

Write

X

50H

Block Erase Setup/Confirm

2

5 Write BA

20H Write BA

D0H

Full Chip Erase Setup/Confirm

2

Write

X

30H Write

X

D0H

Word/Byte Write Setup/Write

2

5,6 Write WA

40H Write WA

WD

Alternate Word/Byte Write

Setup/Write

2

5,6 Write WA

10H Write WA

WD

Multi Word/Byte Write

Setup/Confirm

≥4

9 Write WA

E8H Write WA

N-1

Block Erase and (Multi)

Word/byte Write Suspend

1

5 Write

X

B0H

Confirm and Block Erase and

(Multi) Word/byte Write Resume

1

5 Write

X

D0H

Block Lock-Bit Set Setup/Confirm

2

7 Write BA

60H Write BA

01H

Block Lock-Bit Reset

Setup/Confirm

2

8 Write

X

60H Write

X

D0H

STS Configuration

Level-Mode for Erase and Write

2

Write

X

B8H Write

X

00H

(RY/BY# Mode)

STS Configuration

Pulse-Mode for Erase

2

Write

X

B8H Write

X

01H

STS Configuration

Pulse-Mode for Write

2

Write

X

B8H Write

X

02H

STS Configuration

Pulse-Mode for Erase and Write

2

Write

X

B8H Write

X

03H

NOTES:

1. BUS operations are defined in Table 3 and Table 3.1.

2. X=Any valid address within the device.

IA=Identifier Code Address: see Figure 4.

QA=Query Offset Address.

BA=Address within the block being erased or locked.

WA=Address of memory location to be written.

3. SRD=Data read from status register. See Table 14 for a description of the status register bits.

WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high

first).

ID=Data read from identifier codes.

QD=Data read from query database.

4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status

codes. See Section 4.2 for read identifier code data.

5. If the block is locked, WP# must be at VIH to enable block erase or (multi) word/byte write operations. Attempts

to issue a block erase or (multi) word/byte write to a locked block while RP# is VIH.

6. Either 40H or 10H are recognized by the WSM as the byte write setup.

7. A block lock-bit can be set while WP# is VIH.

8. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block

lock-bits.

9. Following the Third Bus Cycle, inputs the write address and write data of ’N’ times. Finally, input the confirm

command ’D0H’.

10. Commands other than those shown above are reserved by SHARP for future device implementations and

should not be used.

Rev. 2.0

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