AT91SAM9G10-CU Просмотр технического описания (PDF) - Atmel Corporation

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AT91SAM9G10-CU

AT91 ARM Thumb-based Microcontrollers

Atmel Corporation 

AT91SAM9G10

8.1.1

Internal Memory Mapping

Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap

status and the BMS state at reset.

Table 8-3. Internal Memory Mapping

Address

Master 0: ARM926 Instruction

REMAP(RCB0) = 0

REMAP (RCB0) = 1

0x0000 0000

BMS = 1

Int. ROM

BMS = 0

EBI NCS0(1)

Int. RAM C

Master 1: ARM926 Data

REMAP (RCB1) = 0

BMS = 1

BMS = 0

Int. ROM

EBI NCS0(1)

REMAP (RCB1) = 1

Int. RAM C

Note: 1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC

Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.

8.1.1.1

Internal SRAM

The AT91SAM9G10 embeds a high-speed 16-Kbyte SRAM.

8.1.1.2

Internal ROM

The AT91SAM9G10 integrates a 32-Kbyte Internal ROM mapped at address 0x0040 0000. It is

also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset.

8.1.1.3

USB Host Port

The AT91SAM9G10 integrates a USB Host Port Open Host Controller Interface (OHCI). The

registers of this interface are directly accessible on the AHB Bus and are mapped like a standard

internal memory at address 0x0050 0000.

8.1.1.4

LCD Controller

The AT91SAM9G10 integrates an LCD Controller. The interface is directly accessible on the

AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.

8.1.2

Boot Strategies

The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,

the memory layout can be configured with two parameters.

REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This

is done by software once the system has booted for each Master of the Bus Matrix. Refer to the

Bus Matrix Section for more details.

When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an

external memory. This is done via hardware at reset.

Note: Memory blocks not affected by these parameters can always be seen at their specified base

addresses. See the complete memory map presented in Figure 8-1 on page 15.

The AT91SAM9G10 Bus Matrix manages a boot memory that depends on the level on the BMS

pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is

reserved for this purpose.

If BMS is detected at 1, the boot memory is the embedded ROM.

If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the

External Bus Interface.

17

6462A–ATARM–03-Jun-09

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