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AT91SAM9G10-CU Просмотр технического описания (PDF) - Atmel Corporation

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производитель
AT91SAM9G10-CU
Atmel
Atmel Corporation Atmel
AT91SAM9G10-CU Datasheet PDF : 730 Pages
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AT91SAM9G10
9.2 Reset Controller
• Based on two Power-on-Reset cells
• Status of the last reset
– Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset
• Controls the internal resets and the NRST pin output
9.3 Shutdown Controller
• Shutdown and Wake-up logic:
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
9.4 General-purpose Backup Registers
• Four 32-bit general-purpose backup registers
9.5 Clock Generator
• Embeds the Low-power 32,768 Hz Slow Clock Oscillator
– Provides the permanent Slow Clock to the system
• Embeds the Main Oscillator
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
• Embeds Two PLLs
– Outputs 80 to 300 MHz clocks
– Integrates an input divider to increase output accuracy
– 1 MHz minimum input frequency
• Provides SLCK, MAINCK, PLLACK and PLLBCK.
Figure 9-2. Clock Generator Block Diagram
XIN32
XOUT32
Clock Generator
Slow Clock
Oscillator
XIN
XOUT
Main
Oscillator
Slow Clock
SLCK
Main Clock
MAINCK
PLLRCA
PLL and
Divider A
PLLA Clock
PLLACK
PLLRCB
PLL and
Divider B
PLLB Clock
PLLBCK
Status Control
Power
Management
Controller
21
6462A–ATARM–03-Jun-09

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