AT91SAM9R64(2008) Просмотр технического описания (PDF) - Atmel Corporation

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Компоненты Описание

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AT91SAM9R64
(Rev.:2008)

AT91 ARM Thumb Microcontrollers

Atmel Corporation 

6.5 Shutdown Logic Pins

The SHDN pin is an output only, which is driven by the Shutdown Controller only at low level. It

can be tied high with an external pull-up resistor at VDDBU only.

The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.

7. Processor and Architecture

7.1 ARM926EJ-S Processor

• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java

acceleration

• Two Instruction Sets

– ARM High-performance 32-bit Instruction Set

– Thumb High Code Density 16-bit Instruction Set

• DSP Instruction Extensions

• 5-Stage Pipeline Architecture:

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

– Data Memory (M)

– Register Write (W)

• 4-Kbyte Data Cache, 4-Kbyte Instruction Cache

– Virtually-addressed 4-way Associative Cache

– Eight words per line

– Write-through and Write-back Operation

– Pseudo-random or Round-robin Replacement

• Write Buffer

– Main Write Buffer with 16-word Data Buffer and 4-address Buffer

– DCache Write-back Buffer with 8-word Entries and a Single Address Entry

– Software Control Drain

• Standard ARM v4 and v5 Memory Management Unit (MMU)

– Access Permission for Sections

– Access Permission for large pages and small pages can be specified separately for

each quarter of the page

– 16 embedded domains

• Bus Interface Unit (BIU)

– Arbitrates and Schedules AHB Requests

– Separate Masters for both instruction and data access providing complete Matrix

system flexibility

– Separate Address and Data Buses for both the 32-bit instruction interface and the

32-bit data interface

– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit

(Words)

18 AT91SAM9R64/RL64 Preliminary

6289A–ATARM–15-Jan-08

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