AT91SAM9R64(2008) Просмотр технического описания (PDF) - Atmel Corporation

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AT91SAM9R64
(Rev.:2008)

AT91 ARM Thumb Microcontrollers

Atmel Corporation 

AT91SAM9R64/RL64 Preliminary

The voltage ranges are determined by programming registers in the Chip Configuration registers

located in the Matrix User Interface.

At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either

1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the

device out of its Slow Clock Mode.

The PIO lines are supplied through VDDIOP and the speed of the signal that can be driven on

them can reach 50 MHz with 50 pF load.

6. I/O Line Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.

TDO is an output, driven at up to VDDIOP, and have no pull-up resistor.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It

integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left uncon-

nected for normal operations.

All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU.

6.2 Test Pin

The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-

nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal

operations. Driving this line at a high level leads to unpredictable results.

This pin is supplied with VDDBU.

6.3 Reset Pins

NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven

with voltage at up to VDDIOP.

As the product integrates power-on reset cells, which manages the processor and the JTAG

reset, the NRST and NTRST pin can be left unconnected.

The NRST and NTRST pins integrates a permanent pull-up resistor of 100 kΩ typical to

VDDIOP.

The NRST signal is inserted in the Boundary Scan.

6.4 PIO Controllers

All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up

resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product

datasheet for more details.

After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which

are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral

at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing

tables.

17

6289A–ATARM–15-Jan-08

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