AD5340(Rev0) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
AD5340
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5340 Datasheet PDF : 20 Pages
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AD5330/AD5331/AD5340/AD5341
AD5341 FUNCTIONAL BLOCK DIAGRAM
AD5341 PIN CONFIGURATION
BUF
GAIN
DB.. 7
DB0
HBEN
CS
WR
CLR
LDAC
INTER-
FACE
LOGIC
POWER-ON
RESET
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
RESET
VREF
VDD
AD5341
DAC
REGISTER
12-BIT
DAC
BUFFER
VOUT
POWER-DOWN
LOGIC
HBEN 1
20 DB7
BUF 2
VREF 3
19 DB6
18 DB5
VOUT 4
GND 5
12-BIT
AD5341
17 DB4
16 DB3
CS
6
TOP VIEW 15
(Not to Scale)
DB2
WR 7
14 DB1
GAIN 8
13 DB0
CLR 9
12 VDD
LDAC 10
11 PD
Pin
No.
Mnemonic
1
HBEN
2
3
4
5
6
7
8
9
10
11
12
13–20
BUF
VREF
VOUT
GND
CS
WR
GAIN
CLR
LDAC
PD
VDD
DB0–DB7
PD GND
AD5341 PIN FUNCTION DESCRIPTIONS
Function
High Byte Enable Pin. This pin is used when writing to the device to determine if data is written
to the high byte register or the low byte register.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
–8–
REV. 0
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