NLVSX4373MUTAG Просмотр технического описания (PDF) - ON Semiconductor
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NLVSX4373MUTAG Datasheet PDF : 12 Pages
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NLSX4373
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 3 and 4)
Symbol
Parameter
VL = 1.5 V, VCC = 5.5 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL
I/O VL Risetime
tFVL
I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
Test Conditions
Min
Typ
Max Unit
15 ns
20 ns
30 ns
10 ns
20 ns
20 ns
5 nS
20
Mb/s
VL = 1.8 V, VCC = 2.8 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL
I/O VL Risetime
tFVL
I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
15 ns
15 ns
25 ns
10 ns
15 ns
15 ns
5 nS
20
Mb/s
VL = 2.5 V, VCC = 3.6 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL
I/O VL Risetime
tFVL
I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
15 ns
10 ns
15 ns
10 ns
15 ns
15 ns
5 nS
20
Mb/s
VL = 2.8 V, VCC = 1.8 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL
I/O VL Risetime
tFVL
I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
25 ns
10 ns
20 ns
15 ns
15 ns
15 ns
5 nS
20
Mb/s
3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C.
4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
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