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78Q2132 Просмотр технического описания (PDF) - TDK Corporation

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78Q2132 Datasheet PDF : 36 Pages
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78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
REGISTER DESCRIPTION
The 2132 implements twenty user accessible 16-bit registers which are accessible through the Station
Management Interface on the MDIO and MDC pins. The supported registers are shown below. Unsupported
registers will be read as all zeros. All of the registers respond to the broadcast address, PHYAD value 00000.
The register map is implemented in two pages, with page 0 being the power-up reset default. Page 0 implements
the standard 802.3 MII registers along with the vendor specific register set. The vendor specific registers 16, 17,
18, 19 are mapped into both pages for convenience and to implement the page selection via bit MR19.0. Page 1
contains the HomePNA specific registers. The MII management 16-bit register set implemented in the 2132 is as
follows:
ADDRESS
Page
SYMBOL
0
0
MR0
1
0
MR1
2
0
MR2
3
0
MR3
4
0
MR4
5
0
MR5
6
0
MR6
7
0
MR7
8-15
0
MR8-15
16
both
MR16
17
both
MR17
18
both
MR18
19
both
MR19
0
1
P1R0
1
1
P1R1
2
1
P1R2
3
1
P1R3
4,5
1
P1R4,5
6,7
1
P1R6,7
Note: MR 3.3:0 contains revision specific data.
NAME
Control
Status
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
(Not implemented, read as zero)
(Reserved, read as zero)
Vendor Specific
Interrupt Control/Status Register
Diagnostic Register
HomePNA Register
HomePNA Control
HomePNA Status
HomePNA IMASK
HomePNA ISTAT
HomePNA TX_PCOM
HomePNA RX_PCOM
RESET VALUE (HEX)
(0000)
(1801)
000E
7121
(0061)
0000
0000
0000
0000
(0141)
0000
(0000)
0000
0004
0000
0000
0000
00000000
00000000
LEGEND
TYPE DESCRIPTION
R Read-able by management
RC Cleared on a read operation
0/1 Default value upon power-up or reset
TYPE DESCRIPTION
W Write-able by management
SC Self clearing, write-able
(0/1) Default value dependent on pin setting. The value in
brackets indicates typical case.
In above table, the (xxxx) denotes that some of the bit values are determined by pin settings, and so, the default
may be a bit different.
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