AD14160/AD14160LBB-4 Просмотр технического описания (PDF) - Analog Devices
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AD14160/AD14160LBB-4 Datasheet PDF : 52 Pages
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AD14160/AD14160L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
Parameter
40 MHz–5 V
Min
Max
40 MHz–3.3 V
Min
Max
Units
Timing Requirements:
tSSDATI Data Setup Before CLKIN
3.5 + DT/8
3.5 + DT/8
ns
OBSOLETE tHSDATI
tDAAK
tSACKC
tHACKC
Data Hold After CLKIN
ACK Delay After Address,
MSx, SW, BMS1, 2
ACK Setup Before CLKIN2
ACK Hold After CLKIN
Switching Characteristics:
tDADRO
Address, MSx, BMS, SW Delay
After CLKIN1
tHADRO Address, MSx, BMS, SW Hold
After CLKIN
tDPGC
tDRDO
tDWRO
tDRWL
tSDDATO
tDATTR
tDADCCK
PAGE Delay After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN3
ADRCLK Delay After CLKIN
3.5 – DT/8
7 + DT/4
–1 – DT/4
13 + 7 DT/8 + W
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
8 – DT/8
16.5 + DT/8
5 – DT/8
5 – 3DT/16
13.5 + DT/4
20 + 5DT/16
8 – DT/8
10.5 + DT/8
3.5 – DT/8
7 + DT/4
–1 – DT/4
ns
13 + 7 DT/8 + W ns
ns
ns
8 – DT/8
ns
–1 – DT/8
ns
9 + DT/8
16.5 + DT/8
ns
–2 – DT/8
5 – DT/8
ns
–3 – 3DT/16 5 – 3DT/16
ns
8 + DT/4
13.5 + DT/4
ns
20 + 5DT/16
ns
0 – DT/8
8 – DT/8
ns
4 + DT/8
10.5 + DT/8
ns
tADRCK
ADRCLK Period
tCK
tCK
ns
tADRCKH ADRCLK Width High
(tCK/2 – 2)
(tCK/2 – 2)
ns
tADRCKL ADRCLK Width Low
(tCK/2 – 2)
(tCK/2 – 2)
ns
W = (number of Wait states specified in WAIT register) × tCK.
NOTES
1For MSx, SW, BMS, the falling edge is referenced.
2ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC.
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
–20–
REV. A
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