AD14160/AD14160LBB-4 Просмотр технического описания (PDF) - Analog Devices
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AD14160/AD14160LBB-4 Datasheet PDF : 52 Pages
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AD14160/AD14160L
Parameter
Clock Input
Timing Requirements:
tCK
tCKL
tCKH
tCKRF
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
40 MHz–5 V
Min
Max
25
100
7
5
3
40 MHz–3.3 V
Min
Max
25
100
8.75
5
3
Units
ns
ns
ns
ns
tCK
CLKIN
OBSOLETE tCKH
tCKL
Figure 9. Clock Input
Parameter
40 MHz–5 V
Min
Max
40 MHz–3.3 V
Min
Max
Units
Reset
Timing Requirements:
tWRST
RESET Pulsewidth Low1
4tCK
4tCK
ns
tSRST
RESET Setup Before CLKIN High2 14.5 + DT/2 tCK
14.5 + DT/2 tCK
ns
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after
reset.
CLKIN
RESET
tWRST
tSRST
Figure 10. Reset
Parameter
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup Before CLKIN High1
tHIR
IRQ2-0 Hold Before CLKIN High1
tIPW
IRQ2-0 Pulsewidth2
NOTES
1Only required for IRQx recognition in the following cycle.
2Applies only if tSIR and tHIR requirements are not met.
40 MHz–5 V
Min
Max
18 + 3DT/4
2 + tCK
12 + 3DT/4
CLKIN
IRQ2-0
tSIR
tHIR
tIPW
Figure 11. Interrupts
–16–
40 MHz–3.3 V
Min
Max
18 + 3DT/4
12 + 3DT/4
2 + tCK
Units
ns
ns
ns
REV. A
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