AD14160/AD14160LBB-4 Просмотр технического описания (PDF) - Analog Devices

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AD14160/AD14160LBB-4

Quad-SHARC DSP Multiprocessor

Analog Devices 

AD14160/AD14160L

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the AD14160/

AD14160L is the bus master accessing external memory space.

These switching characteristics also apply for bus master syn-

chronous read/write timing (see Synchronous Read/Write—Bus

Master). If these timing requirements are met, the synchronous

read/write timing can be ignored (and vice versa).

Parameter

Min

Timing Requirements:

tDAAK

tDSAK

ACK Delay from Address, Selects1, 2

ACK Delay from WR Low1

40 MHz–5 V

Max

40 MHz–3.3 V

Min

Max

Units

13 + 7DT/8 + W

7 + DT/2 + W

13 + 7DT/8 + W ns

7 + DT/2 + W ns

OBSOLETE Switching Characteristics:

tDAWH

Address, Selects to WR Deasserted2 16 + 15DT/16 + W

16 + 15DT/16 + W

ns

tDAWL

Address, Selects to WR Low2

2 + 3DT/8

2 + 3DT/8

ns

tWW

WR Pulsewidth

12 + 9DT/16 + W

12 + 9DT/16 + W

ns

tDDWH

Data Setup Before WR High

6 + DT/2 + W

6 + DT/2 + W

ns

tDWHA

Address Hold After WR Deasserted 0 + DT/16 + H

0 + DT/16 + H

ns

tDATRWH Data Disable After WR Deasserted3 0.5 + DT/16 + H 7 + DT/16 + H 0.5 + DT/16 + H 7 + DT/16 + H ns

tWWR

WR High to WR, RD, DMAGx Low 7.5 + 7DT/16 + H

7.5 + 7DT/16 + H

ns

tDDWR

Data Disable Before WR or RD Low 4 + 3DT/8 + I

4 + 3DT/8 + I

ns

tWDE

WR Low to Data Enabled

–1.5 + DT/16

–1.5 + DT/16

ns

tSADADC Address, Selects to ADRCLK High2 –0.5 + DT/4

–0.5 + DT/4

ns

W = (number of wait states specified in WAIT register) × tCK.

H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

NOTES

1ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC.

2For MSx, SW, BMS, the falling edge is referenced.

3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx , SW

BMS

WR

DATA

ACK

tDAWL

tDAWH

tWW

tWDE

tDAAK

tDSAK

tDDWH

tDWHA

tDATRWH

tWWR

tDDWR

RD , DMAG

ADRCLK

(OUT)

tSADADC

Figure 15. Memory Write—Bus Master

REV. A

–19–

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