RF2131 Просмотр технического описания (PDF) - RF Micro Devices

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RF2131

HIGH EFFICIENCY AMPS/ETACS AMPLIFIER

RF Micro Devices 

RF2131

Theory of Operation and Application Information

The RF2131 is a two-stage device with 25dB gain at

full power. Therefore, for +31dBm output power, the

drive required to fully saturate the output is +6dBm.

Based upon HBT (Heterojunction Bipolar Transistor)

2

technology, the part requires only a single positive

4.8V supply to operate to full specification. Bias control

is provided through a single pin interface, and the final

stage ground is achieved through the large pins on

both sides of the package. First stage ground is

brought out through a separate ground pin for isolation

from the output. These grounds should be connected

directly with vias to the PCB ground plane. The output

is brought out through the 4 output pins, and combined

off-chip to form the RF output signal path.

The amplifier operates in Class AB bias mode. The

final stage is "deep AB", meaning the quiescent current

is very low, around 40mA. As the RF drive is

increased, the final stage self-biases, causing the bias

point to shift up and, at full power, draws about 340mA.

The optimum load for the output stage is approximately

10Ω. This is the load at the output collector, and is cre-

ated by the series inductance formed by the output

bond wires, leads, and microstrip, and a shunt capaci-

tor external to the part. With this match, a 50Ω terminal

impedance is achieved. The input is matched to 50Ω

with just a blocking capacitor needed. This data sheet

defines the configuration for AMPS operation, but the

output load may be modified slightly for ETACS opera-

tion. In any case the optimum load for 1.2W is the

same at the device, and only the reactive elements

must change to perform the transformation from 50Ω

down to 10Ω.

The input is DC coupled; thus, a blocking cap must be

inserted in series. Also, the first stage bias may be

adjusted by a resistive divider with high value resistors

on this pin to VPC and ground. For nominal operation,

however, no external adjustment is necessary as inter-

nal resistors set the bias point optimally.

VCC2 provides supply voltage to the first stage, as well

as provides some frequency selectivity to tune to the

operating band. Essentially, the bias is fed to this pin

through a short microstrip. A bypass capacitor sets the

inductance seen by the part, so placement of the

bypass cap can affect the frequency of the gain peak.

For ETACS, the capacitor placement is slightly different

than for AMPS due to the frequency shift. This supply

should be bypassed individually with 33pF or 100pF

capacitors before being combined with VCC for the out-

2-102

put stage to prevent feedback and oscillations.

The RF OUT pins provide the output power. Pins 10

and 11 should be combined externally with pins 14 and

15 with a symmetric combiner, as shown in the PCB

layout. Care should be taken to ensure that the output

paths are symmetric up to the point of combining. This

prevents "odd-mode" cancellation from occurring

wherein one side may get out-of-phase with the other,

affecting efficiency and stability. Bias for the final stage

is fed to this output line, and the feed must be capable

of supporting the approximately 400mA of current

required. Care should also be taken to keep the losses

low in the bias feed and output components. DC losses

in the bias choke will degrade efficiency and power.

The part will operate over a 4.0V to 4.8V range. If, for

example, the full power is desired at minimum voltage,

then the load can be optimized at that point. This is

illustrated in Application Schematic 2. At that point, the

specified efficiency and power should be attainable. As

the voltage is increased, however, the output power will

increase. Thus, in a system design, the ALC (Auto-

matic Level Control) Loop will back down the power to

the desired level. This will occur at a less-than-opti-

mum efficiency, since the load is optimized for mini-

mum voltage. If the load is set up to optimize power

and efficiency at nominal operating voltage, then max

efficiency should be attainable there. This case is illus-

trated in Application Schematic 1. As the voltage drops

to minimum, power will degrade, but the efficiency

tends to be maintained. For nominal 31.5dBm at 4.8V

setup, as the voltage drops to 4.0V, the output power

drops to 30.5dBm with a constant VPC.

The HBT breakdown voltage is >20V, so nominally at

4.8V there should be no issue with overvoltage. Under

extreme conditions, however, which can occur in a cel-

lular handset environment, the supply voltage could be

as high as 7.5V to 8.5V. These conditions may corre-

spond to operation in a battery charger, especially with

the battery removed, which "unloads" the supply cir-

cuit. To add to this worst-case scenario, the RF drive

may be at full power during transmit, and the output

VSWR could be extremely high, corresponding to a

broken or removed antenna. Under all of the above

conditions, the peak RF voltages could well exceed two

times the supply voltage, forcing the device into break-

down. The RF2131 includes overvoltage protection

diodes at the output, which begin clipping the wave-

form peaks at approximately 15V. This protects the

device’s output from breaking down under these worst-

Rev B4 010417

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