RF2131 Просмотр технического описания (PDF) - RF Micro Devices
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RF2131 Datasheet PDF : 10 Pages
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RF2131
Pin Function Description
Interface Schematic
1
PC
Power Control. When this pin is "low", all circuits are shut off. A "low" is
VCC1
typically 0.5V or less at room temperature. During normal operation
this pin is the power control. Control range varies from about 2V for
0dBm to 3.6V for +31dBm RF output power. The maximum power that
PC
To Bias
can be achieved depends on the actual output matching; see the appli-
Stages
cation information for more details.
80 Ω
2
2
NC
Not connected.
3
VCC2
Power supply for the driver stage and interstage matching. A shunt
capacitor is required for tuning the interstage to the proper frequency.
The value of this capacitor depends on the operating frequency and
power level. See the application information for details.
VCC2
RF IN
From Bias
Stages
4
GND
Ground connection. Keep traces physically short and connect immedi-
ately to the ground plane for best performance.
5
GND
Same as pin 4.
6
GND1
Ground connection for the driver stage. Keep traces physically short See pin 1 schematic.
and connect immediately to the ground plane for best performance. It is
recommended to use separate vias to the ground plane for this return
path.
7
RF IN
RF Input. This is a 50Ω input, but the actual impedance depends on the See pin 3 schematic.
interstage matching network connected to pin 3. An external DC block-
ing capacitor is required if this port is connected to a DC path to ground
or a DC voltage.
8
VCC1
Power supply for the bias circuits. An external RF bypass capacitor is See pin 1 schematic.
required. Keep the traces to the capacitor as short as possible, and
connect the capacitor immediately to the ground plane.
9
NC
This pin is not connected internally; however it needs to be connected
to ground externally. This will improve performance by reducing cou-
pling between pins.
10
RF OUT RF Output and power supply for the output stage. The four output pins
are combined, and bias voltage for the final stage is provided through
these pins. The external path must be kept symmetric until combined to
ensure stability. An external matching network is required to provide the
optimum load impedance; see the application schematics for details.
RF OUT
From Bias
Stages
11
RF OUT Same as pin 10.
See pin 10 schematic.
12
GND
Ground connection for the output stage. Keep traces physically short
and connect immediately to the ground plane for best performance.
13
GND
Ground connection for the output stage. Keep traces physically short
and connect immediately to the ground plane for best performance.
14
RF OUT Same as pin 10.
See pin 10 schematic.
15
RF OUT Same as pin 10.
See pin 10 schematic.
16
NC
This pin is not connected internally, however it needs to be connected
to ground externally. This will improve performance by reducing cou-
pling between pins.
Rev B4 010417
2-101
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