V96BMC Просмотр технического описания (PDF) - Unspecified

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V96BMC

HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx® PROCESSORS

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V96BMC Rev.D

V3 Semiconductor retains the rights to change documentation, specifications, or device

functionality at any time without notice. Please verify that you have the latest copy of all

documents before finalizing a design.

1.0 Product Codes

Table 1: Product Codes

Product Code

V96BMC-33LP

V96BMC-40LP

Processor

i960Cx/Hx/Jx

i960Cx/Hx/Jx

Bus Type

32-bit multiplexed/

demultiplexed

32-bit multiplexed/

demultiplexed

Package Frequency

132-pin PQFP 33MHz

132-pin PQFP 40MHz

2.0 Pin Description and Pinout

Table 2 below lists the pin types found on the V96BMC. Table 3 describes the function of each pin on

the V96BMC. Table 4 lists the pins by pin number. Figure 1 shows the pinout for the 132-pin PQFP

package and Figure 2 shows the mechanical dimensions of the package.

Pin Type

I/O12

I

O12

O12-3

Table 2: Pin Types

Description

TTL I/O pin with 12 mA output drive

TTL input only pin

TTL Output pin with 12 mA output drive

TTL Output pin with 12 mA output drive that can be

configured for either 5 volt or 3.3 volt signaling, These

outputs can be configured for 3.3V operation by

connecting the Vcc3 power pins to a 3.3V power plane

(Vcc should always be connected to a 5V supply). Vcc3

can also be connected to the 5V plane if 5V signaling is

desired.

2

V96BMC Rev D Data Sheet Rev 3.2

Copyright © 1998, V3 Semiconductor Inc.

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