V96BMC Просмотр технического описания (PDF) - Unspecified

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Компоненты Описание

производитель

V96BMC

HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx® PROCESSORS

Unspecified 

V96BMC Rev.D

PCLK

ADS

ADDR

R/W

BLAST

READY

AA11:0

RASA

CASA

AB11:0

RASB

CASB

LEA

Mode 0, 1

LEB

Mode 0, 1

LEA

Mode 2, 3

LEB

Mode 2, 3

CEA, TXA

CEB, TXB

Figure 6: Burst Access Timing

0

1

2

3

4

5

6

7

8

9

10

Address N

tARA1

Row

Col

tBSAV

Col+2

tRSH

tARA1

Row

tLED

Col

tBSAV

Col+2

tRSH

tLED

>0 ns

5.0 Revision History

Table 12: Revision History

Revision

Number

3.2

Date

7/98

Comments and Changes

V96BMC Rev D timing parameters with 3.3V DRAM support.

3.1

10/96 Data Book revision.

3.0

05/96

Updated timings to final D-step values.

Simplified data sheet format.

2.0

7/92 Updated timings to final A-step values.

1.0

7/92

First pre-silicon revision of preliminary data sheet.

DC and AC specs TBD. Sent only to a limited number of customers

USA:

2348G Walsh Ave.

Santa Clara CA 95051

Phone: (408)988-1050 Fax: (408)988-2601

Toll Free: (800)488-8410 (Canada and U.S. only)

World Wide Web: http://www.vcubed.com

14

V96BMC Rev D Data Sheet Rev 3.2

Copyright © 1998, V3 Semiconductor Inc.

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