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V96BMC Datasheet PDF : 14 Pages
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V96BMC Rev.D
Table 11: Timing Parameters for V96BMC Vcc=5 Volts +/- 5% and Vcc3= 5 or
3.3 8Volts +/- 5%
Symbol
Description
tC
tCH
tCL
tSU
tH
tH
tRZH
tRHL
tRLH
tRHZ
tBHL
tBLH
tEHL
tELH
tIHL
tILH
tARA1
PCLK period
PCLK high time
PCLK low time
Synchronous input setup
Synchronous input hold
Synchronous input hold (RESET#)
READY 3-state to valid delay
READY synchronous assertion delay
READY synchronous de-assertion delay
READY valid to 3-state delay
BTERM synchronous assertion delay
BTERM synchronous de-assertion delay
BERR synchronous assertion delay
BERR synchronous de-assertion delay
INT synchronous assertion delay
INT synchronous de-assertion delay
Address Input to Row Address output delay
(Interleaved)
tARA2 Address Input to Row Address output delay
(Non-interleaved)
tRAH
tCAV
tCAH
tBCAV
Row address hold from RAS assertion
Column address valid from RAS assertion
Column address hold from CAS assertion
Column address valid delay from previous
CAS assertion (Burst)
tRHL
tRLH
tRAS
tRSH
tRP
tCHL
tCLH
tCAS
tCPN
tRCD
tWESU
PCLK to RAS asserted delay
PCLK to RAS de-asserted delay
RAS pulse width
RAS hold from last CAS assertion
RAS precharge time
PCLK to CAS asserted delay
PCLK to CAS de-asserted delay
CAS pulse width
CAS precharge time
RAS to CAS delay time
Write Enable setup to RAS assertion
Note
1
1
33 MHz
Min Max
30
12
12
9
1
3
3 13
3 13
3 13
3 10
3 14
3 13
3 13
3 12
3 13
3 12
3 14
40 MHz
Min Max Units
25
ns
11
ns
11
ns
8
ns
0.5 ns
3 ns
3 10 ns
3 11 ns
3 11 ns
3
7 ns
3 12 ns
3 11 ns
3 11 ns
3 10 ns
3 11 ns
3 10 ns
3 12 ns
4 18 4 15 ns
2
tM tM+2 tM tM+2 ns
2 tM+1 tM+4 tM+1 tM+4 ns
tC
tC
ns
tC+3
tC+3 ns
3 13 3 11 ns
3 13 3 11 ns
3 3tC-1
3tC-1
ns
4
tN
tN
ns
5 tP-2
tP-2
ns
1
3 13 3 12 ns
4 12 3 11 ns
4 tN-1
tN-1
ns
0.5tC
0.5tC
ns
1.5tC-2 1.5tC 1.5tC-2 1.5tC ns
10
9
ns
Copyright © 1998, V3 Semiconductor Corp.
V96BMC Rev D Data Sheet Rev 3.2
11
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