TDA19978AHV Просмотр технического описания (PDF) - NXP Semiconductors.

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TDA19978AHV

Quad HDMI 1.3a receiver interface with equalizer (HDTV up to 1080p, up to UXGA for PC formats)

NXP Semiconductors. 

NXP Semiconductors

TDA19978A

Quad HDMI 1.3a receiver with digital processing

8.10 Packet extraction

Information sent during the Data Island periods are extracted from the HDMI data stream.

Audio clock regeneration, general control and InfoFrames can be read using the I2C-bus

while audio samples are sent to the audio FIFO.

The TDA19978A can receive the new HDMI 1.3a packets, general control and color

gamut metadata info packets.

In audio applications, the TDA19978A manages HBR packets for high bit rate

compressed audio streams (IEC 61937), One Bit Audio samples and DST packets for

One Bit Audio and SACD with DSD and DST audio streams.

The TDA19978A includes a two channel status decoder supporting multi-channel

reception for Audio Sample Packets. This enables the user to obtain channel status

information from the IEC 60958/IEC 61937 stream such as:

• The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958)

• Copyright protection

• Sampling frequency

Refer to IEC 60958/IEC 61937 specifications for more details.

An update of each InfoFrame or the channel status content is indicated by a register bit

and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary.

8.11 Audio PLL

The TDA19978A generates a 128/256/512 × fs system clock enabling the use of simple

audio DACs without an integrated PLL, such as the UDA1334BTS. The programming of

the audio PLL can be either automatic, using the audio clock regeneration parameters

found in the Data Islands or set manually using the I2C-bus.

All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz,

96 kHz and 192 kHz are accepted by the device.

8.12 Audio formatter

Audio samples can be output in either S/PDIF, I2S-bus formats or DSD (SACD). In I2S-bus

or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins

(AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using the

these pins. The audio port mapping depends on the channel allocation (see Table 4,

Table 5 and Table 6 for detailed information). In the following tables, all ports are LV-TTL

compatible

TDA19978A_3

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 03 — 16 April 2010

© NXP B.V. 2010. All rights reserved.

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