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TDA19978AHV

Quad HDMI 1.3a receiver interface with equalizer (HDTV up to 1080p, up to UXGA for PC formats)

NXP Semiconductors. 

NXP Semiconductors

TDA19978A

Quad HDMI 1.3a receiver with digital processing

8.19 4:2:2 formatter

The 4:2:2 formatter contains the YCbCr 4:2:2 semi-planar and the YCbCr 4:2:2

ITU-R BT.656 formatting functions. The selection of these functions is made using the

I2C-bus.

• In YCbCr 4:2:2 mode: the data frequency for the Y signal is equal to the pixel clock

frequency. While the data frequency for the Cb and Cr signals is equal to half the pixel

clock frequency

• In semi-planar mode: the output clock should be the same as the pixel clock

• In ITU-R BT.656 mode: the data frequency should be the same as the formatter clock

frequency (e.g. pixel clock × 2)

The Start Active Video (SAV) and End Active Video (EAV) timing reference codes can be

included in the data stream based on the HREF, VREF and FREF positions from the

VHREF timing generator.

Specific codes programmed using the I2C-bus can replace the data stream during the

blanking period to mask gain and clamp calibration.

8.20 Video port selection

Each channel can be allocated to a specified video port using the I2C-bus (see Section 13

“Output video port formats (mapping examples)” on page 21) to optimize board layout at

the interface with video processing ICs. For example:

• R, G or B in RGB 4:4:4 mode on VP[29:20]

• Y, Cb or Cr in YUV 4:4:4 mode on VP[19:10]

• Y or Cb-Cr in 4:2:2 semi-planar mode on VP[9:0]

• Cb-Y-Cr-Y in 4:2:2 ITU-R BT.656 mode on VP[9:0]

Each video port can be set to high-impedance using the I2C-bus.

8.21 Output buffers

The levels of the output buffers are LV-TTL compatible. Switching the outputs between

active and high-impedance is set using the I2C-bus.

The outputs HREF, VREF and FREF can be set to high-impedance (Z) or forced LOW (L),

independently of the timing reference codes.

8.22 VHREF timing generator

The VHREF timing generator outputs all of the timing signals used by the device:

• VREF, HREF and FREF signals for SAV, EAV and active video area definition

• VS and HS to change width and position compared with the HDMI inputs

8.23 I2C-bus serial interface

The I2C-bus serial interface enables the internal registers of the device to be

programmed. The slave address of the device is selected by pin A0.

TDA19978A_3

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 03 — 16 April 2010

© NXP B.V. 2010. All rights reserved.

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