PEB20321 Просмотр технического описания (PDF) - Siemens AG

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PEB20321

Multichannel Network Interface Controller for HDLC MUNICH32X

Siemens AG 

PEB 20321

Introduction

Table 1

PCI Bus Interface Pins (cont’d)

Pin No. Pin No. Symbol I/O

P-MQFP- P-TQFP-

160-1

176-1

11

13

PERR s/t/s

12

14

SERR o/d

139

153

REQ

t/s

138

152

GNT

t/s

137

151

CLK

I

Function

Parity Error

When activated, indicates a parity error

over the AD(31:0) and C/BE(3:0) signals

(compared to the PAR input). It has a delay

of two CLK cycles with respect to AD and

C/BE(3:0) (i.e., it is valid for the cycle

immediately following the corresponding

PAR cycle).

PERR is asserted relative to the rising edge

of CLK.

System Error

The MUNICH32X asserts this signal to

indicate a fatal system error.

SERR is activated on the rising edge of

CLK.

Request

Used by the MUNICH32X to request control

of the PCI.

REQ is activated on the rising edge of CLK.

Grant

This signal is asserted by the arbiter to

grant control of the PCI to the MUNICH32X

in response to a bus request via REQ. After

GNT is asserted, the MUNICH32X will

begin a bus transaction only after the

current bus Master has deasserted the

FRAME signal.

GNT is sampled on the rising edge of CLK.

Clock

Provides timing for all PCI transactions.

Most PCI signals are sampled or output

relative to the rising edge of CLK. The

actual clock frequency is either equal to the

frequency of CLK, or CLK frequency

divided by 2. The maximum CLK frequency

is 33 MHz.

Semiconductor Group

19

1998-08-01

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