PEB 20321
Introduction
Table 1
PCI Bus Interface Pins (cont’d)
Pin No. Pin No. Symbol I/O
P-MQFP- P-TQFP-
160-1
176-1
6
8
IRDY
s/t/s
7
9
TRDY s/t/s
Function
Initiator Ready
IRDY indicates the bus master’s ability to
complete the current data phase of the
transaction. It is used in conjunction with
TRDY. A data phase is completed on any
clock where both IRDY and TRDY are
sampled asserted. During a write, IRDY
indicates that valid data is present on
AD(31:0). During a read, it indicates the
master is prepared to accept data. Wait
cycles are inserted until both IRDY and
TRDY are asserted together.
When MUNICH32X is Master, IRDY is an
output.
When MUNICH32X is Slave, IRDY is an
input.
IRDY is updated and sampled on the rising
edge of CLK.
Target Ready
TRDY indicates a slave’s ability to complete
the current data phase of the transaction.
During a read, TRDY indicates that valid
data is present on AD(31:0). During a write,
it indicates the target is prepared to accept
data.
When MUNICH32X is Master, TRDY is an
input.
When MUNICH32X is Slave, TRDY is an
output.
TRDY is updated and sampled on the rising
edge of CLK.
Semiconductor Group
17
1998-08-01