MT90222 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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производитель

MT90222

T1/E1/J1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT90222/3/4

Data Sheet

MT90224 Pin Description (continued)

Pin #

Name I/O

Description

AF13

RXRingClk

AF14

RXRingSync

AC16,AE16,

AF16,AC15,

AE15,AF15,

AD14,AE14

RXRingData

[7:0]

AC1

Clk

C19

LatchClk

A4

Reset

D7

TCK

A5

TMS

B6

TDI

C6

TDO

B5

TRST

AD1

Test1

D19

Test2

C7

Test3

B4

Test4

E2,H1,J1,M3,

P2,T3,Y2,AB3,AE

6,AF8,

AD12,AD15,

AC19,AD25,

AA25,V26,

N25,H26,F26,A2

3,D20,C16,A13,A

8,C5

AA23,AB04,

AC06,AC13,

AC17,AC22,

D6,D10,D14,

D22,E23,F4,

K23,N4,P23, U4

VDD5

V3.3

I TDM Ring RX Clock. Clock input signal used to align the RXRingSync and

RXRingData. Should be connected to the TXRingClk input of the previous MT90224

device in the Ring. There is an internal weak pull-down on this input. NOT 5 V

TOLERANT.

I TDM Ring RX Sync. Synchronization input signal used to retrieve data and control

from the bytes on RXRingData. Should be connected to the TXRingSync output of

the previous MT90224 device in the Ring. There is an internal weak pull-down on

this input. NOT 5 V TOLERANT.

I TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX TDM

Ring port. Should be connected to the TXRingData inputs of the previous MT90224

device in the Ring. There are internal weak pull-downs on these inputs. NOT 5 V

TOLERANT.

System Signals

I System Clock (50 MHz nominal). In the MT90224, this clock is used for all internal

operations of the device.

I Counter Latch Clock. The clock present at this input can be divided internally to

produce the latch signal for the internal counters. Refer to the Counter Transfer

Command register for more details. This pin has an internal pull-down.

I System Reset. This is an active low input signal. It causes the device to enter the

initial state. The Clk signal must be active to reset the internal registers.

I JTAG Test Clock. TCK should be pulled down if not used.

I JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.

I JTAG Test Data Input. This pin has an internal weak pull-down.

O JTAG Test Data Output. Note: TDO is tristated by TRST pin.

I JTAG Test Reset (active low). Should be asserted LOW on power-up and during

reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal

weak pull-down.

I Test1. Must be tied Low

O Test2. Must be left not connected (NC).

I Test3. Must be pulled up to V3.3 for normal operation. NOT 5 V TOLERANT.

O Test4. Must be left not connected (NC)

Power Signals

S 5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt signals,

otherwise, connect to a 3.3 Volt supply.

S 3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.

29

Zarlink Semiconductor Inc.

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