M38C30E1AXXXFP Просмотр технического описания (PDF) - Renesas Electronics

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M38C30E1AXXXFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

List of figures

Fig. 48 Time up to execution of interrupt processing routine ............................................... 1-47

Fig. 49 A-D conversion equivalent circuit ................................................................................. 1-49

Fig. 50 A-D conversion timing chart .......................................................................................... 1-49

CHAPTER 2 APPLICATION

Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2

Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8) ........................................................ 2-3

Fig. 2.1.3 Structure of port P7 ..................................................................................................... 2-3

Fig. 2.1.4 Structure of Port P0 direction register and port P1 direction register ................. 2-4

Fig. 2.1.5 Structure of Port Pi direction register (i = 2, 4, 5, 6, 8) ....................................... 2-4

Fig. 2.1.6 Structure of Port P7 direction register ...................................................................... 2-5

Fig. 2.1.7 Structure of PULL register A ...................................................................................... 2-5

Fig. 2.1.8 Structure of PULL register B ...................................................................................... 2-6

Fig. 2.1.9 Structure of Port P8 output selection register ......................................................... 2-6

Fig. 2.2.1 Memory map of registers relevant to timers .......................................................... 2-10

Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6) ....................................................................... 2-11

Fig. 2.2.3 Structure of Timer 2 .................................................................................................. 2-11

Fig. 2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-12

Fig. 2.2.5 Structure of Timer 12 mode register ....................................................................... 2-12

Fig. 2.2.6 Structure of Timer 34 mode register ....................................................................... 2-13

Fig. 2.2.7 Structure of Timer 56 mode register ....................................................................... 2-13

Fig. 2.2.8 Structure of Timer A register (low-order, high-order) ........................................... 2-14

Fig. 2.2.9 Structure of Compare register (low-order, high-order) .......................................... 2-14

Fig. 2.2.10 Structure of Timer A mode register ...................................................................... 2-15

Fig. 2.2.11 Structure of Timer A control register .................................................................... 2-15

Fig. 2.2.12 Structure of Interrupt request register 1 ............................................................... 2-16

Fig. 2.2.13 Structure of Interrupt request register 2 ............................................................... 2-17

Fig. 2.2.14 Structure of Interrupt control register 1 ................................................................ 2-18

Fig. 2.2.15 Structure of Interrupt control register 2 ................................................................ 2-18

Fig. 2.2.16 Timers connection and setting of division ratios ................................................. 2-20

Fig. 2.2.17 Relevant registers setting ....................................................................................... 2-21

Fig. 2.2.18 Control procedure ..................................................................................................... 2-22

Fig. 2.2.19 Peripheral circuit example ....................................................................................... 2-23

Fig. 2.2.20 Timers connection and setting of division ratios ................................................. 2-23

Fig. 2.2.21 Relevant registers setting ....................................................................................... 2-24

Fig. 2.2.22 Control procedure ..................................................................................................... 2-24

Fig. 2.2.23 Judgment method of valid/invalid of input pulses ............................................... 2-25

Fig. 2.2.24 Relevant registers setting ....................................................................................... 2-26

Fig. 2.2.25 Control procedure ..................................................................................................... 2-27

Fig. 2.2.26 Timers connection and setting of division ratios ................................................. 2-28

Fig. 2.2.27 Relevant registers setting ....................................................................................... 2-29

Fig. 2.2.28 Control procedure ..................................................................................................... 2-30

Fig. 2.2.29 PWM output and IGBT output (1) ......................................................................... 2-31

Fig. 2.2.30 PWM output and IGBT output (2) ......................................................................... 2-31

Fig. 2.2.31 PWM output and IGBT output (3) ......................................................................... 2-32

Fig. 2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-33

Fig. 2.3.2 Structure of Serial I/O control register 1 ................................................................ 2-33

Fig. 2.3.3 Structure of Serial I/O control register 2 ................................................................ 2-34

Fig. 2.3.4 Structure of Interrupt request register 1 ................................................................. 2-34

Fig. 2.3.5 Structure of Interrupt control register 1 .................................................................. 2-35

Fig. 2.3.6 Serial I/O connection examples (1) ......................................................................... 2-36

Fig. 2.3.7 Serial I/O connection examples (2) ......................................................................... 2-37

38C3 Group User’s Manual

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