PM4354 Просмотр технического описания (PDF) - PMC-Sierra

Номер в каталоге

Компоненты Описание

производитель

PM4354

FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER/FRAMER

PMC-Sierra 

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

1

FEATURES

• Monolithic device which integrates four, full-featured T1 and E1 framers and T1 and E1 short haul and

long haul line interfaces.

• Software selectable between T1/J1 and E1 operation on a per-device basis.

• Meets or exceeds T1 and E1 shorthaul and longhaul network access specifications including ANSI

T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR-

12 and CTR-13.

• Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.

• Provides receive equalization, clock recovery and line performance monitoring.

• Provides transmit and receive jitter attenuation.

• Provides digitally programmable long haul and short haul line build out.

• Provides four full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers.

• Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI

T1.408 specifications.

• Supports Nx64Kbit/s fractional bandwidth backplane.

• Supports transfer of PCM data to/from 1.544MHz and 2.048MHz system-side devices. Also supports

a fractional T1 or E1 system interface with independent backplane receive/backplane transmit

Nx64Kbit/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock

gapping.

• Supports 8.192 Mbit/s, H-100 compatible, H-MVIP on the system interface for all T1 or E1 links, a

separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8.192

Mbit/s H-MVIP system interface for all T1 or E1 CCS, V5.1/V5.2, and GR.303 channels.

• Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing

and redundancy.

• Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and Nx64Kbit/s

rates as recommended in ITU-T O.151 and O.152.

• Provides robbed bit signaling extraction and insertion on a per-DS0 basis.

• Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1

Framer, the PM4351 COMET E1/T1 transceiver, and the PM8315 TEMUX T1/E1 Framer with

integrated Mapper and M13 MUX.

• Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

1

Share Link: