SST89E554 Просмотр технического описания (PDF) - Silicon Storage Technology
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SST89E554 Datasheet PDF : 58 Pages
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FlashFlex51 MCU
SST89E564 / SST89V564 / SST89E554 / SST89V554
Preliminary Specifications
TABLE 10-4: DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C TO +70°C OR -40°C TO +85°C, 25MHZ DEVICES; 2.7-3.6V; VSS = 0V
Symbol Parameter
Test Conditions
Min
Max Units
VIL
VIH
VIH1
VOL
VOL
VOL1
VOH
VOH1
VBOD
IIL
ITL
ILI
RRST
CIO
IDD
Input Low Voltage
Input High Voltage
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1.5, 1.6, 1.7)
Output Low Voltage (Ports 1, 2, 3)1
Output Low Voltage (Port 0, ALE, PSEN#)1,3
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4
Output High Voltage (Port 0 in External Bus Mode)4
Brown-out Detection Voltage
Logical 0 Input Current (Ports 1, 2, 3)
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
Input Leakage Current (Port 0)
RST Pulldown Resistor
Pin Capacitance6
Power Supply Current7
In-Application Mode
2.7 < VDD < 3.3
-0.5
0.7
V
2.7 < VDD < 3.3
0.2VDD + 0.9 VDD + 0.5 V
2.7 < VDD < 3.3
0.7VDD
VDD + 0.5 V
VDD = 2.7V
IOL = 16mA
1.0
V
VDD = 2.7V
IOL = 100µA2
IOL = 1.6mA2
IOL = 3.5mA2
0.3
V
0.45
V
1.0
V
VDD = 2.7V
IOL = 200µA2
IOL = 3.2mA2
0.3
V
0.45
V
VDD = 2.7V
IOH = -10µA
VDD - 0.3
V
IOH = -30µA
VDD - 0.7
V
IOH = -60µA
VDD - 1.5
V
VDD = 2.7V
IOH = -200µA
VDD - 0.3
V
IOH = -3.2mA
VDD - 0.7
V
2.25
2.55
V
VIN = 0.4V
-1
-75
µA
VIN = 2V
-650
µA
0.45 < VIN < VDD-0.3
±10
µA
225
kΩ
@ 1 MHz, 25°C
15
pF
70
mA
Active Mode
22
mA
Idle Mode
6.5
mA
Standby (Stop Clock) Mode
Tamb = 0°C to +70°C
70
µA
Tamb = -40°C to +85°C
88
µA
Power Down Mode
Minimum VDD = 2V
Tamb = 0°C to +70°C
40
µA
Tamb = -40°C to +85°C
50
µA
T10-4.4 384
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
15mA
Maximum IOL per 8-bit port:
26mA
Maximum IOL total for all outputs: 71mA
If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due
to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.
©2001 Silicon Storage Technology, Inc.
49
S71181-03-000 9/01 384
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