SST89E554 Просмотр технического описания (PDF) - Silicon Storage Technology

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SST89E554

Flash flex 51 MCU

Silicon Storage Technology 

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

TABLE 9-2: POWER SAVING MODES

Mode

Idle Mode

Initiated by

Software

(Set IDL bit in

PCON)

Power Down

Mode

Software

(Set PD bit in

PCON)

Standby (Stop

Clock) Mode

External hardware gates OFF

the external clock input to the

MCU. This gating should be

synchronized with an input

clock transition (low-to-high or

high-to-low).

State of MCU

Exited by

CLK is running.

Enabled interrupt or hardware reset.

Interrupts, serial port and tim- Start of interrupt clears IDL bit and

ers/counters are active. Pro- exits Idle mode, after the ISR RETI

gram Counter is stopped.

instruction, program resumes execu-

ALE and PSEN# signals at a tion beginning at the instruction follow-

HIGH level during Idle. All ing the one that invoked Idle mode. A

registers remain unchanged. user could consider placing two or

three NOP instructions after the

instruction that invokes idle mode to

eliminate any problems. A hardware

reset restarts the device similar to a

power-on reset.

CLK is stopped. On-chip

Enabled external level sensitive inter-

SRAM and SFR data is main- rupt or hardware reset. Start of inter-

tained. ALE and PSEN# sig- rupt clears PD bit and exits Power

nals at a LOW level during Down mode, after the ISR RETI

Power Down. External Inter- instruction program resumes execution

rupts are only active for level beginning at the instruction following

sensitive interrupts, if

the one that invoked Power Down

enabled.

mode. A user could consider placing

two or three NOP instructions after the

instruction that invokes Power Down

mode to eliminate any problems. A

hardware reset restarts the device sim-

ilar to a power-on reset.

CLK is frozen. On-chip SRAM Gate ON external clock. Program exe-

and SFR data is maintained. cution resumes at the instruction fol-

ALE and PSEN# are main- lowing the one during which the clock

tained at the levels prior to was gated off.

the clock being frozen.

T9-2.6 384

©2001 Silicon Storage Technology, Inc.

45

S71181-03-000 9/01 384

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