SST89E554 Просмотр технического описания (PDF) - Silicon Storage Technology

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SST89E554

Flash flex 51 MCU

Silicon Storage Technology 

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

Watchdog Timer Data/Reload Register (WDTD)

Location

7

6

5

4

3

2

1

0

Reset Value

085H

Watchdog Timer Data/Reload

00000000b

Symbol

WDTD

Function

Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set.

SPI Control Register (SPCR)

Location

7

6

D5H

SPIE

SPE

5

DORD

4

MSTR

3

CPOL

2

CPHA

1

SPR1

0

Reset Value

SPR0 00000100b

Symbol

Function

SPIE

If both SPIE and ES are set to one, SPI interrupts are enabled.

SPE

SPI enable bit.

0: Disables SPI.

1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1[4], P1[5], P1[6], P1[7].

DORD

Data Transmission Order.

0: MSB first in data transmission.

1: LSB first in data transmission.

MSTR

Master/Slave select.

0: Selects Slave mode.

1: Selects Master mode.

CPOL

Clock Polarity

0: SCK is low when idle (Active High).

1: SCK is high when idle (Active Low).

CPHA

Clock Phase control bit.

0: Shift triggered on the leading edge of the clock.

1: Shift triggered on the trailing edge of the clock.

SPR1, SPR0 SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured

as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK

and the oscillator frequency, fOSC, is as follows:

SPR1

0

0

1

1

SPR0

0

1

0

1

SCK = fOSC divided by

4

16

64

128

©2001 Silicon Storage Technology, Inc.

21

S71181-03-000 9/01 384

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