SST89E554 Просмотр технического описания (PDF) - Silicon Storage Technology

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SST89E554

Flash flex 51 MCU

Silicon Storage Technology 

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

SuperFlash Status Register (SFST) (Read Only Register)

Location

7

6

5

4

3

0B6H

SECD1 SECD2 SECD3

-

-

2

1

FLASH_BUSY

-

0 Reset Value

-

xxxxx0xxb

Symbol

Function

SECD1

Security bit 1.

SECD2

Security bit 2.

SECD3

Security bit 3.

Please refer to Table 4-6 for security lock options.

FLASH_BUSYFlash operation completion polling bit.

1: Device is busy with flash operation.

0: Device has fully completed the last command.

SuperFlash Configuration Register (SFCF)

Location

7

6

5

4

3

2

1

0

Reset Value

0B1H

-

IAPEN

-

-

-

-

SWR

BSEL

x0xxxxxxb

Symbol

IAPEN

SWR

BSEL

Function

Enable IAP operation

0: IAP commands are disabled

1: IAP commands are enabled

Software Reset

See “9.2 Software Reset” on page 43

Program memory block switching bit

See Figures 3-1 and 3-2.

SuperFlash Command Register (SFCM)

Location

7

6

5

0B2H

FIE FCM6 FCM5

4

FCM4

3

FCM3

2

FCM2

1

FCM1

0

FCM0

Reset Value

00000000b

Symbol

FIE

FCM[6:0]

Function

Flash Interrupt Enable.

0: INT1# is not reassigned.

1: INT1# is re-assigned to signal IAP operation completion.

External INT1# interrupts are ignored.

Flash operation command

000_1011b Sector-Erase

000_1101b Block-Erase

000_1100b Byte-Verify1

000_1110b Byte-Program

000_1111b Prog-SB1

000_0011b Prog-SB2

000_0101b Prog-SB3

000_1001b Prog-SC0

All other combinations are not implemented, and reserved for future use.

1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.

©2001 Silicon Storage Technology, Inc.

17

S71181-03-000 9/01 384

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