CMX644A Просмотр технического описания (PDF) - CML Microsystems Plc

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CMX644A

V.22 and Bell 212A Modem

CML Microsystems Plc 

V22 and Bell 212A Modem

CMX644A

RX PSK MODE Register ($E8)

(Bit 7)

Reserved for future use. This bit should be set to ‘0’.

CPBW SELECT

(Bit 6)

When this bit is set to ‘1’ the Call Progress Detector bandwidth is

approximately 300Hz - 620Hz.

When this bit is set to ‘0’ the Call Progress Detector bandwidth is

approximately 400Hz - 620Hz.

DE-SCRAMB UNLOCK

(Bit 5)

When this bit is set to ‘1’ the de-scrambler will check for sequences of

64 consecutive ones at its input and once detected it will invert the next

output from the de-scrambler. When this bit is set to ‘0’ the all ones

detection is disabled - it should be set as such until the handshaking

sequence is complete.

DE-SCRAMB ENABLE

(Bit 4)

When this bit is set to ‘1’ the Rx data is passed through the de-

scrambler. When it is set to ‘0’ the de-scrambler is bypassed.

EQUAL ER1 and ER0

(Bits 3 and 2)

These 2 bits control the level of equalisation applied to the received

signal according to the following table:

ER1

ER0

Receiver

(Bit 3) (Bit 2)

Equalisation

0

0

no equalisation

0

1

Low

1

0

Medium

1

1

High

See Figures 5a and 5b for the typical equaliser responses. The equaliser is

automatically powersaved when ET1 and ET0 are set to

“no equalisation” (‘0’, ‘0’).

ENABLE

(Bit 1)

When this bit is set to ‘1’ the PSK receiver is enabled. When it is set to

‘0’ the receiver is disabled. Associated flags are only set when this bit is

‘1’.

HI/LO BAND

(Bit 0)

This bit determines whether the received PSK signal should be filtered

and derived from the low channel (900Hz - 1500Hz) or the high channel

(2100Hz - 2700Hz). When this bit is set to ‘0’ the low channel is

selected. When it is set to ‘1’ the high channel is selected.

© 2000 Consumer Microcircuits Limited

16

D/644A/6

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