CMX644A Просмотр технического описания (PDF) - CML Microsystems Plc

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CMX644A

V.22 and Bell 212A Modem

CML Microsystems Plc 

V22 and Bell 212A Modem

CMX644A

TX DATA BYTE Register ($E3)

The bytes of data to be transmitted should be loaded into this register. It is double buffered, thus giving the

user up to 8 bit periods to load in the next 8 bits. Each byte represents 4 lots of 2 consecutive bits (dibits) with

the most significant dibit being loaded first (taking Bit 7 of this register as being the most significant). The

data is reversed so that it is transmitted least significant dibit first. These dibits represent a transmitted phase

change according to the following table:

Dibit values

00

01

11

10

Phase change

+ 90°

0°

+ 270°

+ 180°

Note that the left-hand digit of the dibit is

the one occurring first in the data stream

as it enters the modulator portion of the

modem after the scrambler.

UART MODE Register ($E4)

(Bit 7 and Bit 6)

Reserved for future use. These bits should be set to ‘0’.

SYNC/ASYNC

(Bit 5)

When this bit is ‘0’, data will be transmitted and received in normal 8 bit

mode without modification.

When this bit is ‘1’, data will be transmitted and received with one start

bit (‘0’) and 7/8 bits, odd/even parity, 0 or 1 or 2 stop bits according to

the remainder of the bits in this register.

Prior to handshaking the UART Mode register needs Bit 5 cleared for

synchronous operation. After the handshaking procedure has

completed Bit 5 the UART Mode register should be set for

asynchronous data transfer. The remaining bits of this register should

be configured to be compatible with the modem you are talking to.

The minimum number of stop bits only applies to the transmitter, the

receiver does not require any defined number of stop bits.

STOP BITS A and B

(Bits 4 and 3)

The minimum number of stop bits transmitted after each data byte plus

parity is defined by the table below.

PARITY ENABLE

(Bit 2)

Stop Bits

A

0

0

1

1

Stop Bits

B

0

1

0

1

Number of

Stop Bits

0

1

1

2

The receiver does not require any defined number of stop bits.

When this bit is ‘1’ an extra bit is added after the data to indicate the

parity of that data.

When set to ‘0’, parity is disabled. This bit affects both transmitter and

receiver.

PARITY ODD/EVEN

(Bit 1)

When this bit is ‘1’ the parity is set odd, and when this bit is ‘0’ the parity

is set even.

This bit affects both transmitter and receiver.

DATA BITS 8/7

(Bit 0)

When this bit is ‘1’ the data is set to transmit and receive 7 bits

i.e. bits 0 - 6.

When this bit is ‘0’ the normal 8 bits of data is programmed.

This bit affects both transmitter and receiver.

© 2000 Consumer Microcircuits Limited

14

D/644A/6

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