CMX644A Просмотр технического описания (PDF) - CML Microsystems Plc

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CMX644A

V.22 and Bell 212A Modem

CML Microsystems Plc 

V22 and Bell 212A Modem

CMX644A

GAIN BLOCKS Register ($E2)

Bits 0 to 3 (RG0 to RG3) control the levels of the receiver input gain block according to the following table:

RG3

(Bit 3)

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

RG2

(Bit 2)

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

RG1

(Bit 1)

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

RG0

(Bit 0)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GAIN (dB)

-4.70

-3.46

-2.12

-0.96

0.00

0.87

1.64

2.36

3.08

3.69

4.22

4.76

5.27

5.78

6.21

6.58

The gain should be set in a calibration procedure in order to trim out the effects of any component tolerances

which may give rise to a variation in the Carrier Detect Threshold levels.

Bits 4 to 7 (TG0 to TG3) control the levels of the transmit path gain block according to the following table:

TG3

(Bit 7)

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

TG2

(Bit 6)

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

TG1

(Bit 5)

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

TG0

(Bit 4)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GAIN (dB)

OFF

(o/p at Bias)

-5.6

-5.2

-4.8

-4.4

-4.0

-3.6

-3.2

-2.8

-2.4

-2.0

-1.6

-1.2

-0.8

-0.4

0.0

© 2000 Consumer Microcircuits Limited

13

D/644A/6

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