ATT3042 Просмотр технического описания (PDF) - Unspecified
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ATT3042 Datasheet PDF : 80 Pages
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ATT3000 Series Field-Programmable Gate Arrays
Data Sheet
February 1997
Configuration (continued)
Table 3. ATT3000 Device Configuration Data
Device
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
Gates
1500
2000
3000
4500
6000
CLBs
(row x column)
64
(8 x 8)
100
(10 x 10)
144
(12 x 12)
224
(16 x 14)
320
(20 x 16)
IOBs
Flip-flops
64
80
96
120
144
256
360
480
688
928
Bits-per-frame
75
(with 1 start/3 stop)
92
108
140
172
Frames
197
241
285
329
373
Program Data =
Bits * Frames + 4
(excludes header)
14779
22176
30784
46064
64160
PROM Size (bits) =
Program Data
+ 40-bit Headers
14819
22216
30824
46104
64200
Note: The length count produced by the bit stream generation program = [(40-bit preamble + sum of program data + 1 per daisy-chain device)
rounded up to a multiple of 8] – (2 ≤ K ≤ 4), where K is a function of DONE and RESET timing selected. An additional 8 is added if the
roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
12
24
4
PREAMBLE LENGTH COUNT
DATA FRAME
75
3
STOP
DATA
POSTAMBLE
LAST FRAME
3
STOP
4
3
START
DOUT LEAD DEVICE
HIGH
1/2 CLOCK CYCLE
DELAY FROM DATA INPUT
START
LENGTH COUNT*
WEAK PULL-UP
PROG
I/O ACTIVE
DONE
INTERNAL RESET
5-3111(F)
* The configuration data consists of a composite 40-bit preamble/length count, followed by one or more concatenated FPGA programs,
separated by 4-bit postambles. An additional final postamble bit is added for each slave device, and the result rounded up to byte boundary.
The length count is two less than the number of resulting bits. Timing of the assertion of DONE and termination of the internal RESET may
each be programmed to occur one cycle before or after the I/O outputs become active.
Figure 20. FPGA Configuration and Start-Up
20
Lucent Technologies Inc.
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