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ATT3042

Field-Programmable Gate Arrays

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ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Programmable Interconnect (continued)

Internal Buses

A buffer in the upper left corner of the FPGA chip drives

a global net which is available to all .k inputs of logic

blocks. Using the global buffer for a clock signal pro-

vides a skew-free, high fan-out, synchronized clock for

use at any or all of the I/O and logic blocks. Configura-

tion bits for the .k input to each logic block can select

this global line, or another routing resource, as the

clock source for its flip-flops. This net may also be pro-

grammed to drive the die edge clock lines for IOB use.

An enhanced speed, CMOS threshold, offers direct

access to this buffer and is available at the

second pad from the top of the left die edge.

A buffer in the lower right corner of the array drives a

horizontal long line that can drive programmed connec-

tions to a vertical long line in each interconnection

column. This alternate buffer also has low skew and

high fan-out. The network formed by this alternate buf-

fer’s long lines can be selected to drive the .k inputs of

the logic blocks. CMOS threshold, high-speed access

to this buffer is available from the third pad from the

bottom of the right die edge.

A pair of 3-state buffers is located adjacent to each

CLB. These buffers allow logic to drive the horizontal

long lines. Logical operation of the 3-state buffer

controls allows them to implement wide multiplexing

functions. Any 3-state buffer input can be selected as

drive for the horizontal long line bus by applying a low

logic level on its 3-state control line (see Figure 15A).

The user is required to avoid contention that can result

from multiple drivers with opposing logic levels. Control

of the 3-state input by the same signal that drives the

buffer input creates an open-drain wired-AND function.

A logical high on both buffer inputs creates a high

impedance which represents no contention. A logical

low enables the buffer to drive the long line low (see

Figure 15B). Pull-up resistors are available at each end

of the long line to provide a high output when all con-

nected buffers are nonconducting. This forms fast, wide

gating functions. When data drives the inputs and sep-

arate signals drive the 3-state control lines, these buff-

ers form multiplexers (3-state buses). In this case, care

must be used to prevent contention through multiple

active buffers of conflicting levels on a common line.

Figure 16 shows 3-state buffers, long lines, and pull-up

resistors.

3-STATE

Figure 14. Programmable Interconnection of Long Lines

14

Lucent Technologies Inc.

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