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ATT3042

Field-Programmable Gate Arrays

Unspecified 

ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Configuration (continued)

USER I/O PINS WITH HIGH-IMPEDANCE PULL-UP

INIT = LOW

INITIALIZATION

POWER-ON

TIME DELAY

HDC = HIGH

LDC = LOW

ACTIVE RESET

PWRDWN

INACTIVE

POWERDOWN

NO HDC, LDC

OR PULL-UP

PWRDWN

ACTIVE

CLEAR

CONFIGURATION

MEMORY

RESET

ACTIVE

NO

TEST

MODE PINS

CONFIGURATION

PROGRAM MODE

START-UP

OPERATIONAL

MODE

YES

LOW ON DONE/PROG AND RESET

ACTIVE RESET

OPERATES ON

USER LOGIC

5-3110(F)

Figure 18. State Diagram of Configuration Process for Powerup and Reprogram

Length count control allows a system of multiple

FPGAs in assorted sizes to begin operation in a syn-

chronized fashion. The configuration program gener-

ated by the ORCA Foundry Development System

begins with a preamble of 111111110010 (binary), fol-

lowed by a 24-bit length count representing the total

number of configuration clocks needed to complete

loading of the configuration program(s). The data fram-

ing is shown in Figure 19. All FPGAs connected in

series read and shift preamble and length count in (on

positive) and out (on negative) CCLK edges. An FPGA

which has received the preamble and length count then

presents a HIGH data out until it has intercepted the

appropriate number of data frames. When the configu-

ration program memory of an FPGA is full and the

length count does not compare, the FPGA shifts any

additional data through, as it did for preamble and

length count.

When the FPGA configuration memory is full and the

length count compares, the FPGA will execute a syn-

chronous start-up sequence and become operational

(see Figure 20 on page 20). Two CCLK cycles after the

completion of loading configuration data, the user

I/O pins are enabled as configured. As selected in

ORCA Foundry, the internal user-logic reset is released

either one clock cycle before or after the I/O pins

become active. A similar timing selection is program-

mable for the DONE/PROG output signal. DONE/PROG

may also be programmed to be an open drain or

include a pull-up resistor to accommodate wired-

ANDing. The high during configuration (HDC) and low

during configuration (LDC) are two user I/O pins which

are driven active when an FPGA is in initialization,

clear, or configure states. These signals and DONE/

PROG provide for control of external logic signals such

as reset, bus enable, or PROM enable during

configuration.

For parallel master configuration modes, these signals

provide PROM enable control and allow the data pins

to be shared with user logic signals.

User I/O inputs can be programmed to be either TTL or

CMOS compatible thresholds. At powerup, all inputs

have TTL thresholds and can change to CMOS thresh-

olds at the completion of configuration, if the user has

selected CMOS thresholds. The threshold of PWRDWN

and the direct clock inputs are fixed at a CMOS level.

If the crystal oscillator is used, it will begin operation

before configuration is complete to allow time for

stabilization before it is connected to the internal

circuitry.

18

Lucent Technologies Inc.

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