ADP5020(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADP5020 Datasheet PDF : 28 Pages
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Data Sheet
SWITCHING SPECIFICATIONS
Table 2.
Parameter
SWITCHING FREQUENCY
CH1
CH2
SYNC CLOCK DIVIDER RATIO
SYNC CHARACTERISTICS
Frequency Range
Frequency Duty Cycle
Signal
DC Coupling Level
Low Level Input Voltage
High Level Input Voltage
DC Coupling
AC Coupling Level
AC Coupling Capacitor
Input Current
Symbol Conditions
fSW1
Sync disabled
fSW2
Sync disabled
RATIODIV SYNC_9P6 = 1
RATIODIV SYNC_19P2 = 1
fSYNC1
fSYNC2
fSYNCDUTY
VIL
VIH
VSYNC
VCAC-PP
ISYNC
Sine wave, peak-to-peak
SYNC_9P6 = 1, or SYNC_19P2 = 1
ADP5020
Min
Typ Max
Unit
2.5
3
3.6
MHz
2.5
3
3.6
MHz
3
6
9.6
MHz
19.2
MHz
40
50 60
%
0.7 × VDD_IO
0
0.5
1.0
10
50
0.3 × VDD_IO V
V
VDD_IO
V
VDD_IO
V
nF
µA
DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR
Table 3.
Parameter
Symbol Conditions
Min
Typ
OUTPUT VOLTAGE
Range1
VOUT1
3-bit range
2.5
Initial Accuracy
Total Accuracy
TA = 25°C, VDD12, VOUT1 = 3.3 V, ILOAD = 20 mA −1
VDD13, ILOAD = 50 mA to 600 mA
−5
VOUT1 REGULATION
Load Regulation
Line Regulation
ILOAD = 20 mA to 600 mA
VDDA = 1.8 V, VDD12, 3
0.2
0.15
CURRENT
Maximum Output Current
IBK1MAX
VDD13, VOUT1 = 2.5 V to 3.7 V
Quiescent Current
IQBK1
ILOAD = 0 mA
4
POWER
Low-Side Power nMOSFET
RDSON1
ID = 400 mA
175
High-Side Power pMOSFET
RDSON1
ID = 400 mA
250
SWITCH CURRENT LIMIT
ICL1
0.8
1.2
MINIMUM ON TIME
tMIN1
55
MAXIMUM DUTY CYCLE
DMAX1
88
SOFT START TIME
tSS1
1.4
COUT DISCHARGE SWITCH ON RESISTANCE RDIS1
0.7
1
1 See Table 13 (the BUCK1_VSEL register, Address 0x01) for details.
2 VDD1 = 3.1 V to 5.5 V, ILOAD is less than 200 mA. For tight regulation, the supply voltage must be 0.6 V higher than the output voltage.
3 VDD1 = 3.7 V to 5.5 V, ILOAD is more than 200 mA. For tight regulation, the supply voltage must be 1.2 V higher than the output voltage.
Max
3.7
+1
+4
600
6
250
400
1.6
95
1.3
Unit
V
%
%
%
%
mA
mA
mΩ
mΩ
A
ns
%
ms
kΩ
Rev. A | Page 5 of 28
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