ADP3401 Просмотр технического описания (PDF) - Analog Devices

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ADP3401

GSM Power Management System

Analog Devices 

ADP3401

300

4-LAYER BOARD

␪JA = 60؇C/W

250

200

150

100

VBAT = 5V

VBAT = 5.5V

VBAT = 6V

VBAT = 7V

RTC LDO (VRTC)

The RTC LDO charges a rechargable coin cell to run the real-

time clock module. It has been targeted to charge Manganese

Lithium batteries such as the ML series (ML621/ML1220)

from Sanyo. The ML621 has a small physical size (6.8 mm

diameter) and a nominal capacity of 2.5 mAh, which yields

about 250 hours of backup time.

Figure 18 shows the use of VRTC with the Enhanced GSM

Processor which is a part of the AD20msp425 chipset.

50

0

؊20

0

20

40

60

80 85

AMBIENT TEMPERATURE – ؇C

Figure 16. Total LDO Load Current vs. Temperature and VBAT

Low Dropout Regulators (LDOs)

The ADP3401 high-performance LDOs are optimized for

their given functions by balancing quiescent current, dropout

voltage, line/load regulation, ripple rejection, and output

noise. 2.2 µF tantalum or MLCC ceramic capacitors are

recommended for use with the digital and analog LDOs, and

0.22 µF for the TCXO LDO.

Digital LDO (VCC)

The digital LDO (VCC) supplies all the digital circuitry in the

handset (baseband processor, baseband converter, external

memory, display, etc). The LDO has been optimized for very

low quiescent current (30 µA maximum) at light loads as this

LDO is on at all times. This is due to both the structure of GSM

and a new clocking scheme used in the AD20msp425. Figure 17

shows how the digital current varies as a function of time.

~2ms

0.5s TO 2s

~50mA

~200␮A

TIME

MICROPROCESSOR

START

MICROPROCESSOR

STOP

Figure 17. Digital Power as a Function of Time

Analog LDO (VCCA)

This LDO has the same features as the digital LDO. It has further-

more been optimized for good low frequency ripple rejection for use

with analog sections in order to reject the ripple coming from the RF

power amplifier. VCCA is rated to 130 mA load which is sufficient

to supply the complete analog section of a baseband converter such

as the AD6421/AD6425, including a 32 Ω earpiece. The analog

LDO and the TCXO LDO can be controlled by ANALOGON.

TCXO LDO (VTCXO)

The TCXO LDO is intended as a supply for the temperature-

compensated crystal oscillator, which needs its own ultralow noise

supply. The output current is rated to 5 mA for the TCXO LDO.

ADP3401

VRTC

COIN

CELL

PWRONIN

ENHANCED

GSM PROCESSOR

(AD20msp425)

VRTC

RTC

MODULE

PWRON

Figure 18. Connecting VRTC and POWERONIN to the

AD20msp425 Chipset

The ADP3401 supplies current both for charging the coin cell and

for the RTC module when the digital supply is off. The nominal

charging voltage of 2.85 V ensures charging down to a main

battery voltage of 3.0 V. The inherent current limit of VRTC

ensures long cell life while the precise output voltage regulation

charges the cell to more than 90% of its capacity. In addition, it

features a very low quiescent current (10 µA) since this LDO is

running all the time, even when the handset is switched off. It also

has reverse current protection with low leakage which is needed

when the main battery is removed and the coin cell supplies the

RTC module.

The RTC module has a built-in alarm which, when it expires,

will pull POWERONIN high, allowing an alarm function even if

the handset is switched off.

Reference Output (REFOUT)

The reference output is a low-noise, high-precision reference

with a guaranteed accuracy of 1.5% over temperature. The

reference can be fed to the baseband converter, such as the

AD6425, improving the absolute accuracy of the converters

from 5% to 1.5%. This significantly reduces calibration time

needed for the baseband converter during production.

SIM Interface

The SIM interface generates the needed SIM voltage—either 3 V

or 5 V, dependent on SIM type, and also performs the needed

logic level translation. Quiescent current is low, as the SIM card

will be powered all the time. Note that DATAIO and I/O have

integrated pull-up resistors as shown in Figure 19. See Table II for

the control logic of the charge pump output, VSIM.

–10–

REV. 0

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