IS61LPD25636A Просмотр технического описания (PDF) - Integrated Silicon Solution
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IS61LPD25636A
Integrated Silicon Solution
IS61LPD25636A Datasheet PDF : 33 Pages
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IS61VPD25636a IS61LPD25636a
IS61VPD51218a IS61LPD51218a
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165 PBGA PACKAGE PIN CONFIGURATION
512K x 18 (TOP VIEW)
1
2
A
NC
A
B
NC
A
C
NC
NC
D
NC
DQb
E
NC
DQb
F
NC
DQb
G
NC
DQb
H
NC
Vss
J
DQb
NC
K
DQb
NC
L
DQb
NC
M DQb
NC
N DQPb
NC
P
NC
NC
R MODE NC
3
CE
CE2
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
4
BWb
NC
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
A
5
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
6
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A1*
A0*
7
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDO
TCK
8
ADSC
OE
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
A
9
ADV
ADSP
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol Pin Name
BWE
Byte Write Enable
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
TCK, TDO
TMS, TDI
JTAG Pins
NC
No Connect
DQx
Data Inputs/Outputs
DQPx
Data Inputs/Outputs
Vdd
3.3V/2.5V Power Supply
Vddq
Isolated Output Power Supply
3.3V/2.5V
Vss
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. C1
05/31/2017
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