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IS61LPD25636A

256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STaTIC RaM

Integrated Silicon Solution 

IS61VPD25636a IS61LPD25636a

IS61VPD51218a IS61LPD51218a

® Long-term Support

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119 BGA PACKAGE PIN CONFIGURATION-256K x 36 (TOP VIEW)

1

2

3

4

5

6

7

A

VDDQ

A

B

NC

CE2

A

ADSP

A

A

ADSC

A

A

VDDQ

A

NC

C

NC

A

A

VDD

A

A

NC

D

DQc

DQPc

Vss

E

DQc

DQc

Vss

F

VDDQ

DQc

G

DQc

DQc

Vss

BWc

H

DQc

DQc

Vss

NC

CE

OE

ADV

GW

Vss

Vss

Vss

BWb

Vss

DQPb

DQb

DQb

DQb

DQb

DQb

DQb

VDDQ

DQb

DQb

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQd

DQd

Vss

CLK

Vss

DQa

DQa

L

DQd

DQd

BWd

NC

BWa

DQa

DQa

M

VDDQ

DQd

Vss

BWE

Vss

DQa

VDDQ

N

DQd

DQd

Vss

A1*

Vss

DQa

DQa

P

DQd

DQPd

Vss

A0*

Vss

DQPa

DQa

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC

A

A

A

NC

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A

A0, A1

ADV

ADSP

ADSC

GW

CLK

CE, CE2

BWx (x=a-d)

BWE

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address

Advance

Address Status Processor

Address Status Controller

Global Write Enable

Synchronous Clock

Synchronous Chip Select

Synchronous Byte Write Controls

Byte Write Enable

Symbol

OE

ZZ

MODE

TCK, TDO

TMS, TDI

NC

DQa-DQd

DQPa-Pd

Vdd

Vddq

Vss

Pin Name

Output Enable

Power Sleep Mode

Burst Sequence Selection

JTAG Pins

No Connect

Data Inputs/Outputs

Output Power Supply

Power Supply

Output Power Supply

Ground

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. C1

05/31/2017

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