IS61LPD25636A Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS61LPD25636A

256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STaTIC RaM

Integrated Silicon Solution 

IS61VPD25636a IS61LPD25636a

IS61VPD51218a IS61LPD51218a

® Long-term Support

World Class Quality

256K x 36, 512K x 18

9 Mb SYNCHRONOUS PIPELINED,

DOUBLE CYCLE DESELECT STATIC RAM

JUNE 2017

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth ex-

pansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Double cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LPD: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%

VPD: Vdd 2.5V + 5%, Vddq 2.5V + 5%

• JEDEC 100-Pin TQFP,

119-pin PBGA and 165-pin PBGA package

• Lead-free available

DESCRIPTION

The  ISSI IS61LPD/VPD25636A and IS61LPD/VP-

D51218A are high-speed, low-power synchronous static

RAMs designed to provide burstable, high-performance

memory for communication and networking applications.

The IS61LPD/VPD25636A is organized as 262,144 words

by 36 bits, and the IS61LPD/VPD51218A is organized as

524,288 words by 18 bits. Fabricated with ISSI's advanced

CMOS technology, the device integrates a 2-bit burst

counter, high-speed SRAM core, and high-drive capability

outputs into a single monolithic circuit. All synchronous

inputs pass through registers controlled by a positive-

edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte write

enable (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

Parameter

tkq

Clock Access Time

tkc

Cycle Time

Frequency

250

200

Units

2.6

3.1

ns

4

5

ns

250

200

MHz

Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-

ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. C1

05/31/2017

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