VT82C586B Просмотр технического описания (PDF) - Unspecified

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VT82C586B

PCI Integrated Peripheral Controller

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VT82C586B

Signal Name

SA[15:0] /

DD[15:0]

SA16

LA23/DCS3B#,

LA22/DCS1B#,

LA21/DCS3A#,

LA20/DCS1A#,

LA[19:17] /

DA[2:0]

SD[15:8] /

GPI[15:8] /

GPO[15:8]

SBHE#

IOR#

IOW#

MEMR#

MEMW#

SMEMR#

SMEMW#

BALE

IOCS16#

MEMCS16#

IOCHCK#

IOCHRDY

Pin No.

20-25, 27-28,

36-38, 40-44

19

63-67, 69-70

86-85, 83-80,

78-77

62

12

11

123

124

10

9

35

125

76

5

8

ISA Bus Control

I/O Signal Description

B System Address Bus / IDE Data Bus

B System Address Bus

B Multifunction Pins

ISA Bus Cycles:

Address: The LA[23:17] address lines are bi-directional. These address lines allow

accesses to physical memory on the ISA bus up to 16MBytes.

PCI IDE Cycles:

Chip Select: DCS1A# is for the ATA command register block and corresponds to

CS1FX# on the primary IDE connector. DCS3A# is for the ATA command register

block and corresponds to CS3FX# on the primary IDE connector. DCS1B# is for the

ATA command register block and corresponds to CS17X# on the primary IDE

connector. DCS3B# is for the ATA command register block and corresponds to

CS37X# on the primary IDE connector.

Disk Address: DA[2:0] are used to indicate which byte in either the ATA command

block or control block is being accessed.

B System Data. SD[15:8] provide the high order byte data path for devices residing on

the ISA bus. These pins also function as General Purpose Inputs 15-8 if the

GPIO3_CFG bit is low (pin 92 becomes GPI_RE# for enabling external inputs onto

the SD pins using an external buffer). These pins also function as General Purpose

Outputs 15-8 if the GPIO4_CFG bit is low (pin 136 becomes GPO_WE for control

of an external latch).

B System Byte High Enable. SBHE# indicates, when asserted, that a byte is being

transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during

refresh cycles.

B I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive

data on to the ISA data bus.

B I/O Write. IOW# is the command to an ISA I/O slave device that the slave may

latch data from the ISA data bus.

B Memory Read. MEMR# is the command to a memory slave that it may drive data

onto the ISA data bus.

B Memory Write. MEMW# is the command to a memory slave that it may latch data

from the ISA data bus.

O Standard Memory Read. SMEMR# is the command to a memory slave, under

1MB, which indicates that it may drive data onto the ISA data bus

O Standard Memory Write. SMEMW# is the command to a memory slave, under

1MB, which indicates that it may latch data from the ISA data bus.

O Bus Address Latch Enable. BALE is an active high signal asserted by the

VT82C586B to indicate that the address (SA[19:0], LA[23:17] and the SBHE#

signal) is valid

I 16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to

indicate that they support 16-bit I/O bus cycles.

I Memory Chip Select 16. ISA slaves that are 16-bit memory devices drive this line

low to indicate they support 16-bit memory bus cycles.

I I/O Channel Check. When this signal is asserted, it indicates that a parity or an

uncorrectable error has occurred for a device or memory on the ISA Bus.

I I/O Channel Ready. Devices on the ISA Bus negate IOCHRDY to indicate that

additional time (wait states) is required to complete the cycle.

Revision 1.0 May 13, 1997

-7-

Pinouts

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