UPD77110 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD77110 Datasheet PDF : 80 Pages
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µPD77110, 77111, 77112
• Interrupt
Pin Name
INT1 - INT3
INT4
Pin No.
100-pin
TQFP
80-pin
TQFP
80-pin
FBGA
91 - 89
77 - 75
D4, A3,
B4
88
74
A4
I/O
Function
Input
Input
External maskable interrupt input.
• Detected at the falling edge.
Shared by:
−
WAKEUP
• External data memory interface
Pin Name
X/Y
100-pin
TQFP
99
Pin No.
80-pin
TQFP
−
80-pin
FBGA
−
DA0 - DA14 16 - 2
−
−
D0 - D15
34 - 27,
−
−
24 - 17
MRD
97
−
−
MWR
96
−
−
HOLDRQ
92
−
−
BSTB
94
HOLDAK
93
−
−
−
−
I/O
Function
Shared by:
Output Memory select signal output.
−
(3S)
0: Uses X memory.
1: Uses Y memory.
Output Address bus of external data memory.
−
(3S) • Accesses the external memory.
• Continuously outputs the external memory
address accessed last when the external
memory is not being accessed. Kept low
(0x000) if the external memory is never
accessed after reset.
• DA14 is NC (no connection) and does not
function on the µPD77112.
I/O 16-bit data bus.
−
(3S) • Accesses the external memory.
Output Read output
−
(3S) • External memory read
Output Write output
−
(3S) • External memory write
Input Hold request signal
−
• Input a low level to this pin when the external
device uses the external data memory bus of
the µPD77110 and 77112.
Output Bus strobe signal
−
• This pin goes low when the µPD77110 and
77112 use the external data memory bus.
Output Hold acknowledge signal
−
• This pin goes low when the external device
is enabled to use the external data memory
bus of the µPD77110 and 77112.
Remark Pins marked “3S” under the heading “I/O” go into a high-impedance state in the following conditions:
X/Y, DA0-DA14, MRD, MWR: When the bus is released (HOLDAK = low level)
D0-D15: When the external data memory is not being accessed and when the bus is released
(HOLDAK = low level)
14
Data Sheet U12801EJ4V0DS00
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