UPD77110 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD77110 Datasheet PDF : 80 Pages
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µPD77110, 77111, 77112
1. PIN FUNCTION
Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.
1.1 Pin Function Description
• Power supply
Pin No.
Pin Name 100-pin 80-pin
80-pin
I/O
TQFP
TQFP
FBGA
Function
IVDD
35, 77, 85 31, 63, 71 A5, A7, J5
−
Power to DSP core (+2.5 V)
EVDD
25, 50,
64, 75,
100
10, 20,
40, 50,
60, 80
A1, A9,
E1, E9,
J1, J9
−
Power to I/O pins (+3 V)
GND
1, 26, 36,
51, 65,
76, 78, 86
1, 11, 21,
32, 41,
51, 61,
64, 72
A8, B2,
B5, B7,
E2, E8,
H5, H8,
J2
−
Ground
Shared by:
−
−
−
• System control
Pin Name
CLKIN
CLKOUT
RESET
PLL0
PLL1
PLL2
100-pin
TQFP
74
73
87
53
52
49
Pin No.
80-pin
TQFP
62
59
73
−
−
−
80-pin
FBGA
C7
B8
C4
−
−
−
WAKEUP
88
74
A4
I/O
Function
Shared by:
Input
Output
Input
Input
Input
Input
Input
System clock input
Internal system clock output
Internal system reset signal input
PLL multiple setting input (µPD77110 only)
• Determines the PLL multiple at reset as
followings:
PLL2: PLL1: PLL0:
000 : Selects PLL multiple of ×1.
001 : Selects PLL multiple of ×2.
010 : Selects PLL multiple of ×3.
:
111 : Selects PLL multiple of ×8.
• These pins have no function on the
µPD77111 and 77112 .
Stop mode release signal input.
• When this pin is asserted active, the stop
mode is released. The function of this pin
can be activated or deactivated by a mask
option.
• This pin is always valid on the µPD77110 .
−
−
P2
P3
−
INT4
Data Sheet U12801EJ4V0DS00
13
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