UPD6125A Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD6125A Datasheet PDF : 40 Pages
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µPD6125A, 6126A
14. STANDBY FUNCTION (HALT INSTRUCTION)
The µPD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption,
when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode).
In the standby mode, the program execution stops. However, the contents of the internal registers and the data
memory are all retained.
14.1 STOP Mode (Oscillation Stop HALT Instruction)
In the STOP mode, the operation of the system clock generation circuit (ceramic resonator oscillation circuit) stops.
Therefore, operations requiring the system clock will stop.
If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode
will be initiated, after the timer count down operation is completed.
14.2 HALT Mode (Oscillation Continue HALT Instruction)
The CPU stops its operation, until the HALT release condition is satisfied.
The system clock operation continues in this mode.
14.3 Standby Release Conditions
(1) S-IN input
(2) KI/O input
(3) KI input
(4) Timer count down operation completion
(5) I/O input
(6) KI, I/O input
Remark Either high level or low level can be specified for setting a release condition by input.
Table 14-1. Standby Mode Releasing Condition
D3
D2
D1
D0
0
0
0
0/1 0
0
1
Releasing
Condition
S-IN
K I/O
Remarks
When RL ←A 3 is selected, the standby mode is
always released.
Valid only in the IN mode.
0
1
0
KI
0
0
1
1
Timer
Released when 0.
1
0
0
0/1
1
0
1
1
1
1
0
I/O 0
I/O 1
KI, I/O0, I/O1
Valid only in the IN mode.
Judged as an error and initialized even if one of the
I/O is in OUT mode.
Releasing condition: "0"···Low level detection
"1"···High level detection
Caution µPD6125A is not equipped with I/O10 - I/O13 pins.
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