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UPD6125A Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD6125A Datasheet PDF : 40 Pages
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µPD6125A, 6126A
11.7 S-OUT Pin
By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that
communication is in progress.
The S-OUT pin is a CMOS output pin.
The S-OUT pin goes high on reset.
11.8 S-IN Pin (D0 Bit of P1)
To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is connected
as an input to the LSB of the accumulator. The S-IN pin can be pulled down to the VSS level by a mask option from
within the LSI. In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is
copied to the LSB of the accumulator.
If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no
through current flows internally.
When the RL A instruction is executed, the MSB is copied to the LSB.
When “all clear” is input or on reset, the S-IN pin goes into a high-impedance state.
Figure 11-4. The S-IN Pin Organization
CY
A3
A2
A1
A0
Control
register
S-IN
12

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